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1. 发明授权

US5931957A Support for out-of-order execution of loads and stores in a processor 失效
标题翻译：支持处理器中负载和存储的无序执行
公开(公告)号：US5931957A
公开(公告)日：1999-08-03
申请号：US829669
申请日：1997-03-31
申请人： Brian R Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Brian R Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F9/312 , G06F9/38 , G06F11/00 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3861
摘要： To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.
摘要翻译：为了支持关于存储指令执行无序的加载指令，实现了一种机制来检测（和校正）在逻辑上先前的存储指令之前执行的加载指令的发生，并且其中加载指令接收数据为由存储指令修改之前的位置，以及加载指令的正确数据，包括来自存储指令的字节。另外，为了执行与加载指令无序的存储指令，实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。此外，为了支持相对于彼此执行的无序执行的加载指令，实现一种机制以确保任何一对加载指令（其访问至少一个共同的字节）返回数据与执行加载指令一致为了。

2. 发明授权

US6021467A Apparatus and method for processing multiple cache misses to a single cache line 失效
标题翻译：用于处理多个高速缓存未命中到单个高速缓存行的装置和方法
公开(公告)号：US6021467A
公开(公告)日：2000-02-01
申请号：US713056
申请日：1996-09-12
申请人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0859 , G06F12/0897 , Y02B60/1225
摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.
摘要翻译：一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

3. 发明授权

US6021485A Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching 失效
标题翻译：通过有效/实际数据地址字节匹配，将存储指令结果转发到加载指令，减少停止或刷新
公开(公告)号：US6021485A
公开(公告)日：2000-02-01
申请号：US826854
申请日：1997-04-10
申请人： Kurt Alan Feiste , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Kurt Alan Feiste , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F9/38 , G06F12/00 , G06F9/34
CPC分类号： G06F9/3816 , G06F9/30079 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3863
摘要： In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
摘要翻译：在执行无序调度和执行加载和存储指令的超标量处理器中，当存储指令已经被翻译时，加载指令的加载地址范围包含在存储指令的地址范围内，并且数据与存储指令相关联的可用，则与存储指令相关联的数据被转发到加载指令，使得加载指令可以继续执行而不必被停止或刷新。

4. 发明授权

US6079002A Dynamic expansion of execution pipeline stages 失效
标题翻译：执行流水线阶段的动态扩展
公开(公告)号：US6079002A
公开(公告)日：2000-06-20
申请号：US935573
申请日：1997-09-23
申请人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
发明人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3867 , G06F9/3824
摘要： A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.
摘要翻译：公开了一种使用指定存储器地址的指令访问信息的数据处理系统中的方法和系统。该方法和系统包括向执行单元发出指令并存储从指定地址导出的地址。该方法和系统还包括访问高速缓存以获得信息，使用导出的地址并且响应于指示已经存在高速缓存未命中的信号确定是否存在可用于将指定的地址存储在队列中的位置。根据本文公开的系统和方法，根据需要扩展的原因，本发明允许处理器的动态管道扩展，而不会在组件之间分离该功能，从而提高整体系统性能。

5. 发明授权

US06658555B1 Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline 有权
公开(公告)号：US06658555B1
公开(公告)日：2003-12-02
申请号：US09435077
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F9/3867 , G06F9/3885
摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

6. 发明授权

US06336183B1 System and method for executing store instructions 失效
标题翻译：执行存储指令的系统和方法
公开(公告)号：US06336183B1
公开(公告)日：2002-01-01
申请号：US09259140
申请日：1999-02-26
申请人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
发明人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F9312
CPC分类号： G06F9/3889 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.
摘要翻译：在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

7. 发明授权

US06901540B1 TLB parity error recovery 有权
标题翻译： TLB奇偶校验错误恢复
公开(公告)号：US06901540B1
公开(公告)日：2005-05-31
申请号：US09435868
申请日：1999-11-08
申请人： T. W. Griffith, Jr. , Larry Edward Thatcher
发明人： T. W. Griffith, Jr. , Larry Edward Thatcher
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1016
摘要： A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations. In this embodiment, the load/store unit invokes the address translation unit to translate the effective address only if the effective address misses in the ERAT. The LSU may suitably include an ERAT miss queue (EMQ) adapted to retain an effective address that misses in the ERAT until the address translation unit completes the translation process. In this embodiment, the EMQ is configured to issue a TLB parity error interrupt signal to initiate the TLB parity error interrupt routine. In one embodiment, the TLB interrupt routine loads a data address register (DAR) of the microprocessor with the effective address of the instruction that resulted in the parity error. The TLB interrupt routine may further set a data storage interrupt routine status register (DSISR) to indicate the TLB parity error.
摘要翻译：公开了一种用于处理诸如TLB的地址转换设施中的奇偶校验错误的微处理器，数据处理系统和方法。微处理器包括被配置为生成与加载/存储指令相关联的有效地址的加载/存储单元。一种地址转换单元，适于使用翻译后备缓冲器（TLB）将有效地址转换为实际地址。地址转换单元包括奇偶校验器，其被配置为验证由TLB生成的实际地址的奇偶校验，并且当真实地址包含奇偶校验错误时向该加载存储单元发信号。加载存储单元被配置为响应于来自翻译单元的信号而启动TLB奇偶校验错误中断程序。在一个实施例中，TLB中断例程选择性地使包含奇偶校验错误的TLB条目失效。加载/存储单元优选地包括包含一组地址转换的有效到真实地址表（ERAT）。在本实施例中，加载/存储单元仅在ERAT中的有效地址丢失时才调用地址转换单元来翻译有效地址。 LSU可以适当地包括适于保留在ERAT中遗漏的有效地址的ERAT未命中队列（EMQ），直到地址转换单元完成翻译过程。在本实施例中，EMQ被配置为发出TLB奇偶校验错误中断信号以启动TLB奇偶校验错误中断程序。在一个实施例中，TLB中断例程用导致奇偶校验错误的指令的有效地址加载微处理器的数据地址寄存器（DAR）。 TLB中断程序还可以设置数据存储中断程序状态寄存器（DSISR）以指示TLB奇偶校验错误。

8. 发明授权

US06678807B2 System and method for multiple store buffer forwarding in a system with a restrictive memory model 有权
标题翻译：具有限制性内存模型的系统中多存储缓冲区转发的系统和方法
公开(公告)号：US06678807B2
公开(公告)日：2004-01-13
申请号：US09740803
申请日：2000-12-21
申请人： Bryan D. Boatright , Rajesh Patel , Larry Edward Thatcher
发明人： Bryan D. Boatright , Rajesh Patel , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F9/3826 , G06F9/3834
摘要： The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.
摘要翻译：本发明涉及在具有限制性存储器模型的微处理器系统中使用多存储缓冲器转发。根据本发明的实施例，系统和方法允许由两个或多个存储操作完全覆盖的加载操作以经由存储缓冲器转发来接收数据，从而保持限制性存储器模型的副作用提高处理器性能而不违反限制性内存模式。根据本发明的实施例，一种用于具有限制性存储器模型的系统中的多存储缓冲器转发的方法包括执行多个存储指令，执行加载指令，确定由加载指令寻址的存储器区域与缓存线地址匹配存储器，确定由多个存储指令存储的数据完全覆盖由加载指令寻址的存储器区域，并且向前发送存储区是OK信号。

9. 发明授权

US06463511B2 System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model 有权
标题翻译：用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法
公开(公告)号：US06463511B2
公开(公告)日：2002-10-08
申请号：US09750133
申请日：2000-12-29
申请人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
发明人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30087
摘要： The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.
摘要翻译：本发明涉及锁定存储器指令，更具体地说涉及用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法。根据本发明的实施例，一种用于执行锁定存储器指令的方法包括对锁定存储器指令进行解码，获得要通过加载锁定操作使用的高速缓存行的排他所有权，设置位以指示负载 - 锁定操作对高速缓存行的所有权，并激活侦听检查过程。该方法还包括修改负载数据值并存储修改的负载数据值。该方法还包括确定高速缓存行仍然是独占所有，存储加载数据值，确定高速缓存线不被播放，将修改的加载数据值与加载数据值合并，以及释放要退休的锁定存储器指令。

10. 发明授权

US06336168B1 System and method for merging multiple outstanding load miss instructions 有权
标题翻译：用于合并多个未完成的负载错误指令的系统和方法
公开(公告)号：US06336168B1
公开(公告)日：2002-01-01
申请号：US09259139
申请日：1999-02-26
申请人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1316
CPC分类号： G06F9/30043 , G06F9/3824
摘要： Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.
摘要翻译：在加载存储单元中执行多个加载指令的流水线和并行执行。当第一个加载指令引起高速缓存未命中并继续从系统存储器层次结构检索加载数据时，寻址相同加载数据的第二加载指令将被合并到第一加载指令中，以便从系统内存层次结构返回的数据为发送到注册与第一和第二加载指令相关联的文件。结果，第二加载指令不必等待，直到在数据高速缓存中写入和验证加载数据。

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