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11. 发明授权

US08895426B2 Metal gate transistor, integrated circuits, systems, and fabrication methods thereof 有权
标题翻译：金属栅极晶体管，集成电路，系统及其制造方法
公开(公告)号：US08895426B2
公开(公告)日：2014-11-25
申请号：US12784073
申请日：2010-05-20
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8238 , H01L29/49 , H01L27/092 , H01L21/28 , H01L29/66 , H01L29/78
CPC分类号： H01L29/49 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/66545 , H01L29/66583 , H01L29/78 , H01L29/7833 , H01L2224/16225
摘要： A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
摘要翻译：提供了用于形成金属栅极晶体管的最后一种方法。该方法包括在基底上形成电介质材料内的开口。栅极电介质结构形成在开口内和衬底上。工作功能金属层形成在开口内和栅介质结构之上。在功函数金属层上形成硅化物结构。

12. 发明授权

US08847333B2 Techniques providing metal gate devices with multiple barrier layers 有权
标题翻译：提供具有多个阻挡层的金属栅极器件的技术
公开(公告)号：US08847333B2
公开(公告)日：2014-09-30
申请号：US13224033
申请日：2011-09-01
申请人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuang-Yuan Hsu , Jeff J. Xu
发明人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuang-Yuan Hsu , Jeff J. Xu
IPC分类号： H01L29/76 , H01L29/51 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76846 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。

13. 发明授权

US08704280B2 Semiconductor device with strained channels induced by high-k capping metal layers 有权
标题翻译：具有由高k封盖金属层引起的应变通道的半导体器件
公开(公告)号：US08704280B2
公开(公告)日：2014-04-22
申请号：US13240782
申请日：2011-09-22
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/4966 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/66636 , H01L29/7833 , H01L29/7845 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。该器件包括具有多个源极和漏极特征以形成p沟道和n沟道的半导体衬底。该器件还包括位于半导体衬底上的栅堆叠并且设置在源极和漏极特征之间。栅堆叠包括形成在半导体衬底上的高k（HK）电介质层。在紧邻p沟道的HK电介质层的顶部上形成拉伸应力HK覆盖层，并且在HK介电层的顶部形成压缩应力HKN-功函数（N-WF）金属层靠近n通道。一叠金属栅极层沉积在覆盖层上。

14. 发明授权

US08497528B2 Method for fabricating a strained structure 有权
标题翻译：制造应变结构的方法
公开(公告)号：US08497528B2
公开(公告)日：2013-07-30
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
发明人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

15. 发明申请

US20130078779A1 METAL GATE DEVICE WITH LOW TEMPERATURE OXYGEN SCAVENGING 有权
标题翻译：具有低温氧气的金属门装置
公开(公告)号：US20130078779A1
公开(公告)日：2013-03-28
申请号：US13244358
申请日：2011-09-24
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.
摘要翻译：公开了一种具有金属栅极的半导体器件。该器件包括半导体衬底，半导体衬底上的源极和漏极特征，以及位于半导体衬底上并设置在源极和漏极特征之间的栅极堆叠。栅极堆叠包括界面层（IL）层，形成在半导体衬底上的高k（HK）电介质层，形成在HK电介质层顶部的氧清除金属，由使用低温氧气清除技术，以及沉积在氧清除金属层上的金属栅层的堆叠。

16. 发明申请

US20130075826A1 SEMICONDUCTOR DEVICE WITH STRAINED CHANNELS INDUCED BY HIGH-K CAPPING METAL LAYERS 有权
标题翻译：具有高K吸收金属层诱发的应变通道的半导体器件
公开(公告)号：US20130075826A1
公开(公告)日：2013-03-28
申请号：US13240782
申请日：2011-09-22
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/4966 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/66636 , H01L29/7833 , H01L29/7845 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。该器件包括具有多个源极和漏极特征以形成p沟道和n沟道的半导体衬底。该器件还包括位于半导体衬底上的栅堆叠并且设置在源极和漏极特征之间。栅堆叠包括形成在半导体衬底上的高k（HK）电介质层。在紧邻p沟道的HK电介质层的顶部上形成拉伸应力HK覆盖层，并且在HK介电层的顶部形成压缩应力HKN-功函数（N-WF）金属层靠近n通道。一叠金属栅极层沉积在覆盖层上。

17. 发明申请

US20120091528A1 FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： FIN状势场效应晶体管（FINFET）器件及其制造方法
公开(公告)号：US20120091528A1
公开(公告)日：2012-04-19
申请号：US12906820
申请日：2010-10-18
申请人： Chih-Hao Chang , Jeff J. Xu
发明人： Chih-Hao Chang , Jeff J. Xu
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/0886 , H01L27/12 , H01L29/0642 , H01L29/0847 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成翅片结构，所述翅片结构包括所述半导体衬底上的第一材料部分和所述第一材料部分上的第二材料部分; 在翅片结构的一部分上形成栅极结构，使得栅极结构穿过翅片结构，从而分离翅片结构的源极区域和漏极区域，其中鳍状结构的源极和漏极区域在其间限定通道 ; 从翅片结构的源区和漏区移除第二材料部分; 并且在去除第二材料部分之后，在鳍结构的源极和漏极区域中形成第三材料部分。

18. 发明申请

US20120021589A1 METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH 有权
标题翻译：具有减少电极的半导体器件的制造方法
公开(公告)号：US20120021589A1
公开(公告)日：2012-01-26
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/311 , H01L21/30
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

19. 发明授权

US07989355B2 Method of pitch halving 有权
标题翻译：节距减法的方法
公开(公告)号：US07989355B2
公开(公告)日：2011-08-02
申请号：US12370152
申请日：2009-02-12
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/823828 , H01L21/823871 , Y10S438/947
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.
摘要翻译：本公开提供了一种制造半导体器件的方法，该半导体器件包括在衬底上形成掩模层，在掩模层上形成具有第一虚拟特征和第二虚拟特征的虚设层，形成第一和第二间隔物顶部以覆盖顶部分别形成第一和第二间隔套筒以分别围绕第一和第二虚拟特征的侧面部分，去除第一间隔物顶部和第一虚拟特征，同时保护第二虚拟特征，去除第一间隔套筒的第一端部和第二端部，以形成间隔件翅片，并且使用间隔件翅片作为第一掩模元件并将第二虚拟特征图案化为掩模层作为第二掩模元件。

20. 发明申请

US20110169104A1 METHODS AND APPARATUS OF FLUORINE PASSIVATION 有权
标题翻译：氟化物的方法与装置
公开(公告)号：US20110169104A1
公开(公告)日：2011-07-14
申请号：US12687574
申请日：2010-01-14
申请人： Jeff J. Xu , Liang-Gi Yao , Ta-Ming Kuan
发明人： Jeff J. Xu , Liang-Gi Yao , Ta-Ming Kuan
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/2822 , H01L21/26506 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.
摘要翻译：本公开提供了IC器件制造中氟钝化的方法和装置。在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。还公开了通过这种方法制造的半导体器件。

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