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1. 发明申请

US20120104472A1 FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： FIN状势场效应晶体管（FINFET）器件及其制造方法
公开(公告)号：US20120104472A1
公开(公告)日：2012-05-03
申请号：US12917902
申请日：2010-11-02
申请人： Jeff J. Xu , Chih-Hao Chang
发明人： Jeff J. Xu , Chih-Hao Chang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0886 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。一种示例性方法包括提供半导体衬底; 在半导体衬底上形成第一鳍结构和第二鳍结构; 在所述第一和第二鳍结构的一部分上形成栅极结构，使得所述栅极结构穿过所述第一鳍结构和所述第二鳍结构; 在第一和第二鳍结构的暴露部分上外延生长第一半导体材料，使得第一鳍结构和第二鳍结构的暴露部分合并在一起; 并且在所述第一半导体材料上外延生长第二半导体材料。

2. 发明授权

US08623728B2 Method for forming high germanium concentration SiGe stressor 有权
标题翻译：形成高锗浓度SiGe应激源的方法
公开(公告)号：US08623728B2
公开(公告)日：2014-01-07
申请号：US12831842
申请日：2010-07-07
申请人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
发明人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
IPC分类号： H01L21/336 , H01L21/31 , H01L21/469 , H01L21/00
CPC分类号： H01L29/785 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/18 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66795 , H01L29/7848
摘要： A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
摘要翻译：提供了具有高Ge浓度的SiGe应激源的制造方法。该方法包括：提供具有源极区域，漏极区域和沟道之间的半导体衬底; 在源极区域和/或漏极区域上沉积第一SiGe膜层; 进行低温热氧化，例如高水蒸气压湿氧化，以在第一SiGe层的顶部形成氧化物层，并在第一SiGe膜的底部形成具有高Ge百分比的第二SiGe膜层 Ge层扩散到半导体衬底中; 执行热扩散以从第二SiGe膜层形成SiGe应力源，其中SiGe应力源在通道上提供单轴压缩应变; 并除去氧化物层。在进行氧化之前，可以在第一SiGe膜层上淀积Si覆盖层。

3. 发明授权

US09166022B2 Fin-like field effect transistor (FinFET) device and method of manufacturing same 有权
标题翻译：鳍状场效应晶体管（FinFET）器件及其制造方法
公开(公告)号：US09166022B2
公开(公告)日：2015-10-20
申请号：US12917902
申请日：2010-11-02
申请人： Jeff J. Xu , Chih-Hao Chang
发明人： Jeff J. Xu , Chih-Hao Chang
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。一种示例性方法包括提供半导体衬底; 在半导体衬底上形成第一鳍结构和第二鳍结构; 在所述第一和第二鳍结构的一部分上形成栅极结构，使得所述栅极结构穿过所述第一鳍结构和所述第二鳍结构; 在第一和第二鳍结构的暴露部分上外延生长第一半导体材料，使得第一鳍结构和第二鳍结构的暴露部分合并在一起; 并且在所述第一半导体材料上外延生长第二半导体材料。

4. 发明授权

US08367498B2 Fin-like field effect transistor (FinFET) device and method of manufacturing same 有权
公开(公告)号：US08367498B2
公开(公告)日：2013-02-05
申请号：US12906820
申请日：2010-10-18
申请人： Chih-Hao Chang , Jeff J. Xu
发明人： Chih-Hao Chang , Jeff J. Xu
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/0886 , H01L27/12 , H01L29/0642 , H01L29/0847 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

5. 发明授权

US08497528B2 Method for fabricating a strained structure 有权
标题翻译：制造应变结构的方法
公开(公告)号：US08497528B2
公开(公告)日：2013-07-30
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
发明人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

6. 发明申请

US20120091528A1 FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： FIN状势场效应晶体管（FINFET）器件及其制造方法
公开(公告)号：US20120091528A1
公开(公告)日：2012-04-19
申请号：US12906820
申请日：2010-10-18
申请人： Chih-Hao Chang , Jeff J. Xu
发明人： Chih-Hao Chang , Jeff J. Xu
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/0886 , H01L27/12 , H01L29/0642 , H01L29/0847 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成翅片结构，所述翅片结构包括所述半导体衬底上的第一材料部分和所述第一材料部分上的第二材料部分; 在翅片结构的一部分上形成栅极结构，使得栅极结构穿过翅片结构，从而分离翅片结构的源极区域和漏极区域，其中鳍状结构的源极和漏极区域在其间限定通道 ; 从翅片结构的源区和漏区移除第二材料部分; 并且在去除第二材料部分之后，在鳍结构的源极和漏极区域中形成第三材料部分。

7. 发明授权

US08648400B2 FinFET semiconductor device with germanium (GE) fins 有权
标题翻译： FinFET半导体器件采用锗（GE）鳍片
公开(公告)号：US08648400B2
公开(公告)日：2014-02-11
申请号：US13247507
申请日：2011-09-28
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L29/78
CPC分类号： H01L29/66795
摘要： The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin.
摘要翻译：本发明提供一种FinFET元件。 FinFET元件包括锗-FnFET元件（例如，包括Ge鳍的多栅极器件）。在一个实施例中，装置包括翅片，其具有包括Ge和第二部分的第一部分，位于第一部分下方并且包括绝缘材料（例如，二氧化硅）。可以在翅片上形成栅极结构。

8. 发明授权

US08470659B2 Method for reducing interfacial layer thickness for high-k and metal gate stack 有权
标题翻译：降低高k和金属栅极叠层的界面层厚度的方法
公开(公告)号：US08470659B2
公开(公告)日：2013-06-25
申请号：US13595599
申请日：2012-08-27
申请人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/8249
CPC分类号： H01L29/513 , H01L21/02172 , H01L21/022 , H01L21/28158 , H01L21/28211 , H01L21/283 , H01L29/42364 , H01L29/517 , H01L29/78
摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.
摘要翻译：该描述涉及包括在半导体衬底上形成界面层的方法。该方法还包括蚀刻回界面层。该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层至700℃。该方法还包括在界面层上沉积高k介电材料。

9. 发明授权

US08415718B2 Method of forming epi film in substrate trench 有权
公开(公告)号：US08415718B2
公开(公告)日：2013-04-09
申请号：US12784207
申请日：2010-05-20
申请人： Jeff J. Xu
发明人： Jeff J. Xu
IPC分类号： H01L27/085
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02433 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/3065 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L29/045 , H01L29/16 , H01L29/1608 , H01L29/165 , H01L29/20 , H01L29/32 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

10. 发明授权

US08124537B2 Method for etching integrated circuit structure 有权
标题翻译：集成电路结构蚀刻方法
公开(公告)号：US08124537B2
公开(公告)日：2012-02-28
申请号：US12029834
申请日：2008-02-12
申请人： Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
发明人： Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.
摘要翻译：公开了一种用于蚀刻沟槽内的集成电路结构的方法。待蚀刻的层被施加在结构之上和沟槽内。将CF基聚合物沉积在待蚀刻的层上，随后沉积SiOCl基聚合物的覆盖层。基于CF的聚合物将沟槽的宽度减小到在沟槽底部沉积少量或不存在SiOCl基聚合物的程度。执行O2等离子体蚀刻以在沟槽的底部蚀刻通过CF基聚合物。 O2等离子体蚀刻对SiOCl基聚合物几乎没有影响，因此结构的上表面保持被聚合物覆盖。因此，在随后蚀刻待蚀刻的层期间，这些上表面保持完全保护。

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