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11. 发明申请

US20090134944A1 CAPACITIVE-DEGENERATION DOUBLE CROSS-COUPLED VOLTAGE-CONTROLLED OSCILLATOR 有权
标题翻译：电容式变压器双相交流电压控制振荡器
公开(公告)号：US20090134944A1
公开(公告)日：2009-05-28
申请号：US12114705
申请日：2008-05-02
申请人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.
摘要翻译：提供电容变性双交叉耦合压控振荡器。电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容以增加主交叉振荡单元的负电阻。因此，可以增加最大可获得的振荡频率并降低输入电容。

12. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

13. 发明授权

US07956658B2 Digital lock detector and frequency synthesizer using the same 有权
标题翻译：数字锁定检测器和频率合成器使用相同
公开(公告)号：US07956658B2
公开(公告)日：2011-06-07
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

14. 发明授权

US07852165B2 Capacitive-degeneration double cross-coupled voltage-controlled oscillator 有权
标题翻译：电容变性双交叉电压控制振荡器
公开(公告)号：US07852165B2
公开(公告)日：2010-12-14
申请号：US12114705
申请日：2008-05-02
申请人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.
摘要翻译：提供电容变性双交叉耦合压控振荡器。电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容以增加主交叉振荡单元的负电阻。因此，可以增加最大可获得的振荡频率并降低输入电容。

15. 发明申请

US20100271072A1 DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
标题翻译：使用数字锁定检测器和频率合成器
公开(公告)号：US20100271072A1
公开(公告)日：2010-10-28
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03K5/22 , H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

16. 发明申请

US20100134195A1 CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME 审中-公开
标题翻译：具有可变电容的电容器和包括其的数字控制振荡器
公开(公告)号：US20100134195A1
公开(公告)日：2010-06-03
申请号：US12629742
申请日：2009-12-02
申请人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03B5/12 , H01L27/06
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1265
摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.
摘要翻译：提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个除了第一金属层之外的多个金属层中的金属层。开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

17. 发明授权

US07511581B2 Wide-band multimode frequency synthesizer and variable frequency divider 有权
标题翻译：宽带多模频率合成器和可变分频器
公开(公告)号：US07511581B2
公开(公告)日：2009-03-31
申请号：US11634004
申请日：2006-12-05
申请人： Ja Yol Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim , Sang Heung Lee
发明人： Ja Yol Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim , Sang Heung Lee
IPC分类号： H03L7/00
CPC分类号： H03K23/667 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/193
摘要： A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz. The wide-band multimode frequency synthesizer includes a frequency/phase detector for comparing a frequency and phase of a reference high-frequency signal with a frequency and phase of a feedback high-frequency signal; a charge pump for producing an output current corresponding to the result of the comparison performed by the frequency/phase detector; a loop filter for producing an output voltage corresponding to an accumulated value of the output current of the charge pump; a voltage-controlled oscillator for generating an oscillation signal having a frequency corresponding to the output voltage of the loop filter; and a variable frequency divider for dividing an output signal of the voltage-controlled oscillator by a designated integer value, and outputting the result as a feedback signal, wherein at lease two of an amount of unit pumping charges of the charge pump, an RLC value of the loop filter, an RLC value of the voltage-controlled oscillator, and a divisor value of the variable frequency divider are controlled according to a band.
摘要翻译：提供了使用锁相环（PLL）的宽带多模频率合成器。多频率频率合成器包括多模预分频器，相位检测器/电荷泵，燕子式分频器和具有宽带和低相位噪声特性的开关组LC调谐压控振荡器。多模预分频器以五种模式工作，并将信号分为12 GHz。宽带频率合成器可用于各种领域，例如在2 GHz至9 GHz频率范围内工作的WLAN / HYPERLAN / DSRC / UWB系统。宽带多模频率合成器包括用于将参考高频信号的频率和相位与反馈高频信号的频率和相位进行比较的频率/相位检测器; 用于产生与由频率/相位检测器执行的比较结果相对应的输出电流的电荷泵; 环路滤波器，用于产生与电荷泵的输出电流的累积值相对应的输出电压; 用于产生具有与环路滤波器的输出电压对应的频率的振荡信号的压控振荡器; 以及可变分频器，用于将压控振荡器的输出信号除以指定的整数值，并输出该结果作为反馈信号，其中至少两个电荷泵的单位泵送电荷，RLC值根据频带控制环路滤波器的电压控制振荡器的RLC值和可变分频器的除数值。

18. 发明授权

US08432199B2 Fractional digital PLL with analog phase error compensator 有权
标题翻译：具有模拟相位误差补偿器的分数字数字PLL
公开(公告)号：US08432199B2
公开(公告)日：2013-04-30
申请号：US13310581
申请日：2011-12-02
申请人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0802 , H03L7/085 , H03L2207/50
摘要： Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.
摘要翻译：公开了具有模拟相位误差补偿器的分数字数字锁相环。具有模拟相位误差补偿器的数字锁相环可以通过模拟相位误差补偿器进行分数相位误差检测和补偿，从而降低功耗，功耗噪声和瞬态电流噪声，同时提高相位误差检测分辨率。

19. 发明授权

US08344772B2 Time-to-digital converter and all digital phase-locked loop including the same 有权
标题翻译：时间到数字转换器和所有数字锁相环包括相同的
公开(公告)号：US08344772B2
公开(公告)日：2013-01-01
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

20. 发明授权

US08013641B1 Frequency synthesizer including a digital lock detector 有权
标题翻译：频率合成器包括数字锁定检测器
公开(公告)号：US08013641B1
公开(公告)日：2011-09-06
申请号：US13098332
申请日：2011-04-29
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

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