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11. 发明授权

US06864149B2 SOI chip with mesa isolation and recess resistant regions 有权
标题翻译： SOI芯片具有台面隔离和抗凹陷区域
公开(公告)号：US06864149B2
公开(公告)日：2005-03-08
申请号：US10435286
申请日：2003-05-09
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.
摘要翻译：绝缘体上半导体结构包括衬底和覆盖在衬底上的掩埋绝缘体层。多个半导体岛覆盖在埋层绝缘体层上。半导体岛通过沟槽彼此隔离。多个凹陷区域覆盖在沟槽的下表面处的掩埋绝缘体层。

12. 发明授权

US06815274B1 Resist protect oxide structure of sub-micron salicide process 失效
标题翻译：抗氧化保护亚微米自杀过程的氧化物结构
公开(公告)号：US06815274B1
公开(公告)日：2004-11-09
申请号：US10243414
申请日：2002-09-13
申请人： Ming-Chang Hsieh , Hsun-Chih Tsao , Hung-Chih Tsai , Pin-Shyne Chin
发明人： Ming-Chang Hsieh , Hsun-Chih Tsao , Hung-Chih Tsai , Pin-Shyne Chin
IPC分类号： H01L21337
CPC分类号： H01L21/823835 , H01L21/31111 , H01L21/31144 , H01L21/3143 , H01L21/823814 , H01L29/7833 , Y10S438/95
摘要： In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.
摘要翻译：根据本发明的目的，提供了一种创建电阻保护氧化物（RPO）层的新方法。沉积一层ONO，作为RPO层。对ONO的沉积层进行图案化和湿蚀刻，去除二氧化硅的上层或第一层。将第一层二氧化硅的图案化和蚀刻上部用作硬掩模，以移除采用湿蚀刻的中间层氮化硅层。然后施加湿蚀刻以除去剩余的较低的第二层二氧化硅，完成RPO层的图案化。

13. 发明授权

US08937589B2 Gesture control method and gesture control device 有权
标题翻译：手势控制方法和手势控制装置
公开(公告)号：US08937589B2
公开(公告)日：2015-01-20
申请号：US13603432
申请日：2012-09-05
申请人： Shou-Te Wei , Chia-Te Chou , Hsun-Chih Tsao , Chih-Pin Liao
发明人： Shou-Te Wei , Chia-Te Chou , Hsun-Chih Tsao , Chih-Pin Liao
IPC分类号： G09G5/00
CPC分类号： G06F3/005 , G06F3/017 , G06K9/00355 , G06K9/00375
摘要： A gesture control method includes steps of capturing at least one image; detecting whether there is a face in the at least one image; if there is a face in the at least one image, detecting whether there is a hand in the at least one image; if there is a hand in the at least one image, identifying a gesture performed by the hand and identifying a relative distance or a relative moving speed between the hand and the face; and executing a predetermined function in a display screen according to the gesture and the relative distance or according to the gesture and the relative moving speed.
摘要翻译：手势控制方法包括捕获至少一个图像的步骤; 检测所述至少一个图像中是否存在面部; 如果在所述至少一个图像中存在脸部，则检测所述至少一个图像中是否存在手; 如果在所述至少一个图像中存在手，则识别由手执行的手势并且识别手与脸部之间的相对距离或相对移动速度; 以及根据手势和相对距离或根据手势和相对移动速度在显示屏幕中执行预定功能。

14. 发明申请

US20130278493A1 GESTURE CONTROL METHOD AND GESTURE CONTROL DEVICE 有权
标题翻译：手势控制方法和姿势控制装置
公开(公告)号：US20130278493A1
公开(公告)日：2013-10-24
申请号：US13603432
申请日：2012-09-05
申请人： Shou-Te Wei , Chia-Te Chou , Hsun-Chih Tsao , Chih-Pin Liao
发明人： Shou-Te Wei , Chia-Te Chou , Hsun-Chih Tsao , Chih-Pin Liao
IPC分类号： G09G5/00 , G06K9/00
CPC分类号： G06F3/005 , G06F3/017 , G06K9/00355 , G06K9/00375
摘要： A gesture control method includes steps of capturing at least one image; detecting whether there is a face in the at least one image; if there is a face in the at least one image, detecting whether there is a hand in the at least one image; if there is a hand in the at least one image, identifying a gesture performed by the hand and identifying a relative distance or a relative moving speed between the hand and the face; and executing a predetermined function in a display screen according to the gesture and the relative distance or according to the gesture and the relative moving speed.
摘要翻译：手势控制方法包括捕获至少一个图像的步骤; 检测所述至少一个图像中是否存在面部; 如果在所述至少一个图像中存在脸部，则检测所述至少一个图像中是否存在手; 如果在所述至少一个图像中存在手，则识别由手执行的手势并且识别手与脸部之间的相对距离或相对移动速度; 以及根据手势和相对距离或根据手势和相对移动速度在显示屏幕中执行预定功能。

15. 发明申请

US20080171419A1 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US20080171419A1
公开(公告)日：2008-07-17
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/76 , H01L21/44
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

16. 发明授权

US06979867B2 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US06979867B2
公开(公告)日：2005-12-27
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L23/58
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

17. 发明申请

US20050156238A1 Silicide gate transistors and method of manufacture 失效
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US20050156238A1
公开(公告)日：2005-07-21
申请号：US10753632
申请日：2004-01-08
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/49 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

18. 发明申请

US20130141394A1 ELECTRONIC SYSTEMS AND TRACK DETECTION METHODS 审中-公开
标题翻译：电子系统与跟踪检测方法
公开(公告)号：US20130141394A1
公开(公告)日：2013-06-06
申请号：US13609167
申请日：2012-09-10
申请人： Chia-Te Chou , Shou-Te Wei , Hsun-Chih Tsao
发明人： Chia-Te Chou , Shou-Te Wei , Hsun-Chih Tsao
IPC分类号： G06F3/042
CPC分类号： G06F3/0416 , G06F3/03542 , G06F3/042
摘要： An electronic system is provided, including a writing device, first and second image capturing units and a control module. The writing device has a pen point to write on a writing board, and has a first light-emitting unit to emit a first detection light. The first and second image capturing units are respectively disposed on a first corner and a second corner of the writing board to receive the first detection light in a writing mode, in order to respectively generate first and second image signals. The control module obtains the coordinates of the writing device on the writing board according to the first and second image signals, such that, when the writing device writes on the writing board, the control module determines to operate in the writing mode, and simultaneously records a writing track of the writing device.
摘要翻译：提供了一种电子系统，包括写入装置，第一和第二图像捕获单元和控制模块。写入装置具有写在写板上的笔尖，并且具有发射第一检测光的第一发光单元。第一和第二图像拍摄单元分别设置在书写板的第一角和第二角上，以便以写入模式接收第一检测光，以分别产生第一和第二图像信号。控制模块根据第一图像信号和第二图像信号获得写入装置在书写板上的坐标，使得当写入装置写入书写板时，控制模块确定以书写模式操作，同时记录写入设备的写入轨迹。

19. 发明授权

US07638376B2 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US07638376B2
公开(公告)日：2009-12-29
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

20. 发明授权

US07633127B2 Silicide gate transistors and method of manufacture 有权
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US07633127B2
公开(公告)日：2009-12-15
申请号：US11381649
申请日：2006-05-04
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L23/62
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

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