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1. 发明申请

US20080171419A1 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US20080171419A1
公开(公告)日：2008-07-17
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/76 , H01L21/44
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

2. 发明授权

US07638376B2 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US07638376B2
公开(公告)日：2009-12-29
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

3. 发明申请

US20050230763A1 Method of manufacturing a microelectronic device with electrode perturbing sill 审中-公开
标题翻译：用电极扰动门槛制造微电子器件的方法
公开(公告)号：US20050230763A1
公开(公告)日：2005-10-20
申请号：US10824854
申请日：2004-04-15
申请人： Chien-Chao Huang , Cheng-Kuo Wen , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Kuo Wen , Fu-Liang Yang
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/78
CPC分类号： H01L29/785 , H01L21/823842 , H01L29/41791 , H01L29/7833 , H01L2029/7858
摘要： A method of manufacturing a microelectronic device. The method includes providing a substrate and forming a patterned feature located over the substrate and a plurality of doped regions. The patterned feature also comprises at least one electrode, wherein the electrode is proximate a plurality of doped layers. The method further includes forming a sill located within the electrode, wherein the sill comprising at least one impurity and adapted for modifying an electrical property of at least one member adjacent the electrode.
摘要翻译：一种制造微电子器件的方法。该方法包括提供衬底并形成位于衬底上方的图案化特征以及多个掺杂区域。图案化特征还包括至少一个电极，其中电极接近多个掺杂层。所述方法还包括形成位于所述电极内的基台，其中所述基底包括至少一种杂质并且适于改变邻近所述电极的至少一个构件的电性能。

4. 发明申请

US20060194399A1 Silicide Gate Transistors and Method of Manufacture 有权
标题翻译：硅化物栅晶体管及其制造方法
公开(公告)号：US20060194399A1
公开(公告)日：2006-08-31
申请号：US11381649
申请日：2006-05-04
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

5. 发明申请

US20050156238A1 Silicide gate transistors and method of manufacture 失效
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US20050156238A1
公开(公告)日：2005-07-21
申请号：US10753632
申请日：2004-01-08
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/49 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

6. 发明授权

US07633127B2 Silicide gate transistors and method of manufacture 有权
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US07633127B2
公开(公告)日：2009-12-15
申请号：US11381649
申请日：2006-05-04
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L23/62
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

7. 发明授权

US07067379B2 Silicide gate transistors and method of manufacture 失效
公开(公告)号：US07067379B2
公开(公告)日：2006-06-27
申请号：US10753632
申请日：2004-01-08
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.

8. 发明授权

US07265425B2 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US07265425B2
公开(公告)日：2007-09-04
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

9. 发明申请

US20060102955A1 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US20060102955A1
公开(公告)日：2006-05-18
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L21/338 , H01L31/062
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

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