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11. 发明授权

US5655142A High performance derived local bus and computer system employing the same 失效
标题翻译：高性能派生本地总线和采用相同的计算机系统
公开(公告)号：US5655142A
公开(公告)日：1997-08-05
申请号：US705884
申请日：1996-08-28
申请人： Douglas D. Gephardt , Dan S. Mudgett
发明人： Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F13/38 , G06F13/42 , G06F15/78 , G06F13/24
CPC分类号： G06F13/4217 , G06F13/423 , G06F15/7832
摘要： An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus. A latch is coupled to the multiplexed address/data (A/D) lines of the PCI bus and includes a set of output lines coupled to the address input lines of the externally connected peripheral device. The external latch is latched by the loading signal. The cycle definition signals of the PCI bus are further latched within the external latch to provide memory/IO and read/write signals to the external peripheral device. The data lines of the peripheral device may be connected directly to the multiplexed address/data lines of the PCI bus.
摘要翻译：提供了一种集成处理器，其包括CPU核心，耦合到CPU核心的本地总线以及耦合到本地总线的诸如存储器控制器，直接存储器访问控制器和中断控制器的各种外设。还提供总线接口单元以在CPU本地总线和PCI标准复用的外围总线之间进行接口。 CPU核心，存储器控制器，直接存储器访问控制器，中断控制器和总线接口单元都被并入公共集成电路芯片。还提供了本地总线控制单元，其能够与在PCI总线上执行的某些总线周期同步地产生加载信号和地址选通信号。本地总线控制单元允许通过PCI总线连接与CPU本地总线协议兼容的外部外设。锁存器耦合到PCI总线的复用的地址/数据（A / D）线，并且包括耦合到外部连接的外围设备的地址输入线的一组输出线。外部锁存器被加载信号锁存。 PCI总线的周期定义信号进一步锁存在外部锁存器内，以向外部外围设备提供存储/ IO和读/写信号。外围设备的数据线可以直接连接到PCI总线的复用地址/数据线。

12. 发明授权

US5630099A Non-volatile memory array controller capable of controlling memory banks having variable bit widths 失效
标题翻译：能够控制具有可变位宽度的存储体的非易失性存储器阵列控制器
公开(公告)号：US5630099A
公开(公告)日：1997-05-13
申请号：US166124
申请日：1993-12-10
申请人： James R. MacDonald , Douglas D. Gephardt
发明人： James R. MacDonald , Douglas D. Gephardt
IPC分类号： G06F12/06 , G06F13/40 , G06F12/04
CPC分类号： G06F13/4018
摘要： A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to store BIOS code, and may be implemented using a ROM or flash memory device. The non-volatile memory controller includes a data router, a sequencer, and a set of output latches for routing the 8-bit BIOS code (stored within the 8-bit bank) to selected byte lanes of the local bus and for converting the 8-bit data to 32-bit local bus data. The non-volatile memory controller further supports high performance, 32-bit accesses to the user software stored within the 32-bit banks. If the system designer or user instead must maximize the memory capacity of the computer system, the 8-bit bank of memory may be replaced with a larger 32-bit bank of memory. In this configuration, a control signal is provided to the non-volatile memory controller to indicate that a 32-bit bank is connected rather than an 8-bit bank. The control signal causes the sequencer and the data router to be disabled. When a memory access to the 32-bit bank is executed, the non-volatile memory controller accesses the data within the 32-bit bank and drives the data directly on the CPU local bus.
摘要翻译：提供了一种非易失性存储器控制器，其可直接连接到计算机系统的本地总线，并且允许访问一个或多个32位的ROM组和8位非易失性存储器组。 8位非易失性存储器组可以用于例如存储BIOS代码，并且可以使用ROM或闪速存储器件来实现。非易失性存储器控制器包括数据路由器，定序器和一组输出锁存器，用于将8位BIOS代码（存储在8位存储区中）路由到本地总线的选定字节通道，并用于转换8 位数据传输到32位本地总线数据。非易失性存储器控制器还支持对存储在32位存储区中的用户软件的高性能32位访问。如果系统设计人员或用户必须最大化计算机系统的内存容量，则8位存储器组可能会被更大的32位存储器组替换。在该配置中，向非易失性存储器控制器提供控制信号以指示连接32位存储体而不是8位存储体。控制信号使定序器和数据路由器被禁用。当执行对32位存储区的存储器访问时，非易失性存储器控制器访问32位存储区中的数据，并直接在CPU本地总线上驱动数据。

13. 发明授权

US5598539A Apparatus and method for achieving hot docking capabilities for a dockable computer system 失效
标题翻译：用于实现可停靠的计算机系统的热对接能力的装置和方法
公开(公告)号：US5598539A
公开(公告)日：1997-01-28
申请号：US553196
申请日：1995-11-07
申请人： Douglas D. Gephardt , Scott Swanstrom
发明人： Douglas D. Gephardt , Scott Swanstrom
IPC分类号： G06F13/14 , G06F1/16 , G06F3/00 , G06F13/364 , G06F13/40 , G06F13/20
CPC分类号： G06F1/1632 , G06F13/364 , G06F13/4031 , G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： A dockable computer system is capable of performing hot docking or warm docking. Hot docking refers to an ability to dock when the portable computer or docking station are running at full power. Warm docking refers to an ability to dock when the portable computer and docking station are running in a reduced power state. The dockable computer system employs a docking agent which is capable of quieting (rendering inactive) the buses of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal can be provided from software, a user-actuated switch, or an infrared signal. The docking agent preferably quiets the system bus by idling the system bus or asserting bus ownership or bus mastership over the system bus. The docking agent is able to assert bus ownership or bus mastership over the system bus. Alternatively, the docking agent can perform a software idle subroutine or an interrupt subroutine which idles the system bus. Preferably, the system bus is idled by disabling clock signals to it. Preferably, the docking agent also removes bus ownership requests, interrupt requests, and DMA requests from the station bus and system bus.
摘要翻译：可停放的计算机系统能够进行热对接或热对接。热对接是指当便携式计算机或坞站以全功率运行时停靠的能力。温暖对接是指当便携式计算机和对接站在降低功率状态下运行时停靠的能力。可停靠的计算机系统采用对接代理，其能够响应于通知信号而使便携式计算机和对接站的总线静音（使得无效）。通知信号表示状态从脱离状态到对接状态或从对接状态到解除停止状态的变化。通知信号可以由软件，用户驱动的开关或红外信号提供。对接代理优选地通过使系统总线空转或通过系统总线断言总线所有权或总线主管来对系统总线进行停顿。对接代理能够通过系统总线来显示总线所有权或总线主控权。或者，对接代理可以执行软件空闲子程序或空闲系统总线的中断子程序。优选地，系统总线通过禁止其时钟信号而空转。优选地，对接代理还从站总线和系统总线去除总线所有权请求，中断请求和DMA请求。

14. 发明授权

US5557757A High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效
标题翻译：高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
公开(公告)号：US5557757A
公开(公告)日：1996-09-17
申请号：US190647
申请日：1994-02-02
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , G06F13/4027
摘要： An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
摘要翻译：集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚总线上的集成处理器。辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。不需要用于辅助总线的集成处理器的独立地址和数据线。因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。

15. 发明授权

US5404457A Apparatus for managing system interrupt operations in a computing system 失效
标题翻译：用于管理计算系统中的系统中断操作的装置
公开(公告)号：US5404457A
公开(公告)日：1995-04-04
申请号：US837233
申请日：1992-02-14
申请人： Douglas D. Gephardt , Andrew McBride
发明人： Douglas D. Gephardt , Andrew McBride
IPC分类号： G06F9/48 , G06F13/24 , G06F9/46
CPC分类号： G06F13/24 , Y02B60/1228
摘要： An apparatus for managing system interrupt operations in a computing system including a processing unit and peripheral devices. The apparatus comprises a transmission circuit for transmitting signals which effects operative connection among the peripheral devices and the processing unit; an interrupt drive circuit for generating interrupt signals associated with each peripheral device drives the transmission circuit from a first signal level to a second signal level to effect generating an interrupt signal; and an acknowledge drive circuit for generating an acknowledge signal by the processing unit. Each acknowledge drive circuit drives the transmission circuit from an initial signal level to an indicating signal level to effect generation of an acknowledge signal, and drives the transmission circuit from the indicating signal level to the initial signal level upon termination of the acknowledge signal. In its preferred embodiment, the apparatus provides that no peripheral device can generate an interrupt signal for a predetermined time interval following termination of an acknowledge signal.
摘要翻译：一种用于在包括处理单元和外围设备的计算系统中管理系统中断操作的装置。该装置包括用于发送影响外围设备和处理单元之间的操作连接的信号的传输电路; 用于产生与每个外围设备相关联的中断信号的中断驱动电路将传输电路从第一信号电平驱动到第二信号电平以产生中断信号; 以及用于由处理单元产生确认信号的确认驱动电路。每个应答驱动电路将传输电路从初始信号电平驱动到指示信号电平以产生确认信号，并且在确认信号终止时将传输电路从指示信号电平驱动到初始信号电平。在其优选实施例中，该装置规定，在确认信号终止之后，外围设备可以在预定时间间隔内产生中断信号。

16. 发明授权

US5388218A Apparatus and method for supporting a transfer trapping discipline for a non-enabled peripheral unit within a computing system 失效
标题翻译：用于支持计算系统内的非启用的外围单元的转移捕获规则的装置和方法
公开(公告)号：US5388218A
公开(公告)日：1995-02-07
申请号：US836647
申请日：1992-02-14
申请人： Douglas D. Gephardt , Andrew McBride
发明人： Douglas D. Gephardt , Andrew McBride
IPC分类号： G06F13/14 , G06F13/40 , G06F15/02
CPC分类号： G06F13/4068
摘要： An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled. The invention further comprises a method for managing communications within such a computing system comprising the steps of monitoring the enablement profile; generating a feedback signal representative of the enablement profile; communicating the feedback signal to the processing unit; and configuring the processing unit to respond to the feedback signal to determine whether to employ a transfer trapping discipline.
摘要翻译：一种用于管理包括处理单元和多个外围单元的计算系统内的通信的装置。所述处理单元从所述计算系统内的多个轨迹接收信息，并且根据预定标准响应于所述信息确定启用简档。处理单元响应启用简档以选择性地启用指定的外围单元。该装置包括用于监视启用简档的监视电路; 逻辑电路，用于逻辑地处理所述启用简档并生成表示所述启用简档的反馈信号; 以及用于将来自逻辑电路的反馈信号传送到处理单元的发送电路。处理单元响应于反馈信号以确定是否采用传送陷印规则，从而存储目的地为非启用的外围设备的传输，直到启用了非启用的单元。本发明还包括一种用于管理这种计算系统内的通信的方法，包括以下步骤：监视启用简档; 产生代表启用简档的反馈信号; 将所述反馈信号传送到所述处理单元; 以及配置所述处理单元以响应所述反馈信号以确定是否采用转移捕获规则。

17. 发明授权

US08082438B2 Systems and methods for booting a codec processor over a high definition audio bus 有权
标题翻译：通过高清晰度音频总线启动编解码器处理器的系统和方法
公开(公告)号：US08082438B2
公开(公告)日：2011-12-20
申请号：US12202359
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F9/00 , G06F1/04 , G06F3/00 , G06F13/00 , G06F15/00 , G10L19/00 , G10L21/04 , H05K7/10
CPC分类号： G06F9/4401 , G06F9/4408
摘要： Systems and methods for booting a programmable processor such as a DSP that is incorporated into an HDA codec. The codec and a system memory containing boot program instructions are connected to an HDA bus. In a first mode, the DSP receives boot program instructions via the HDA bus and boots using these instructions. In a second mode, the DSP boots from instructions that are contained in a memory that is connected to the DSP. In one embodiment, the memory connected to the DSP is a component of a plug-in card, and the DSP is configured to determine whether the plug-in card is present, then boot from the memory on the plug-in card if it is present or boot from the system memory via the HDA bus if the plug-in card is not present.
摘要翻译：用于引导可编程处理器（例如并入HDA编解码器的DSP）的系统和方法。编解码器和包含引导程序指令的系统存储器连接到HDA总线。在第一种模式下，DSP通过HDA总线接收引导程序指令，并使用这些指令进行引导。在第二种模式下，DSP从包含在连接到DSP的存储器中的指令引导。在一个实施例中，连接到DSP的存储器是插件卡的组件，并且DSP被配置为确定插件卡是否存在，然后从插件卡上的存储器引导，如果它是如果插件卡不存在，则通过HDA总线从系统存储器中显示或引导。

18. 发明授权

US06219754B1 Processor with decompressed video bus 失效
标题翻译：具有解压缩视频总线的处理器
公开(公告)号：US06219754B1
公开(公告)日：2001-04-17
申请号：US08994489
申请日：1997-12-19
申请人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
发明人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译：在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

19. 发明授权

US6055619A Circuits, system, and methods for processing multiple data streams 失效
标题翻译：用于处理多个数据流的电路，系统和方法
公开(公告)号：US6055619A
公开(公告)日：2000-04-25
申请号：US797232
申请日：1997-02-07
申请人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
发明人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
IPC分类号： G10H7/00 , G06F17/00
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275
摘要： An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.
摘要翻译：公开了一种音频信息处理子系统200，其包括用于同时处理多个音频数据流的流处理器100。处理子系统200还包括耦合到流处理器100的程序存储器202，用于存储用于控制处理系统200的指令和还耦合到流处理器100的数据存储器203/204。另外，提供直接存储器访问电路208用于控制直接存储器访问程序存储器202和数据存储器203/204中的所选择的一个。

20. 发明授权

US5625829A Dockable computer system capable of symmetric multi-processing operations 失效
标题翻译：可对称多处理操作的可移植计算机系统
公开(公告)号：US5625829A
公开(公告)日：1997-04-29
申请号：US276250
申请日：1994-07-18
申请人： Douglas D. Gephardt , Steven L. Belt , Drew J. Dutton
发明人： Douglas D. Gephardt , Steven L. Belt , Drew J. Dutton
IPC分类号： G06F15/173 , G06F1/16 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F1/1632 , G06F13/4036 , G06F13/4081
摘要： A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.
摘要翻译：可停靠的计算机系统能够执行对称的多处理操作。更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。

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