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1. 发明授权

US5404457A Apparatus for managing system interrupt operations in a computing system 失效
标题翻译：用于管理计算系统中的系统中断操作的装置
公开(公告)号：US5404457A
公开(公告)日：1995-04-04
申请号：US837233
申请日：1992-02-14
申请人： Douglas D. Gephardt , Andrew McBride
发明人： Douglas D. Gephardt , Andrew McBride
IPC分类号： G06F9/48 , G06F13/24 , G06F9/46
CPC分类号： G06F13/24 , Y02B60/1228
摘要： An apparatus for managing system interrupt operations in a computing system including a processing unit and peripheral devices. The apparatus comprises a transmission circuit for transmitting signals which effects operative connection among the peripheral devices and the processing unit; an interrupt drive circuit for generating interrupt signals associated with each peripheral device drives the transmission circuit from a first signal level to a second signal level to effect generating an interrupt signal; and an acknowledge drive circuit for generating an acknowledge signal by the processing unit. Each acknowledge drive circuit drives the transmission circuit from an initial signal level to an indicating signal level to effect generation of an acknowledge signal, and drives the transmission circuit from the indicating signal level to the initial signal level upon termination of the acknowledge signal. In its preferred embodiment, the apparatus provides that no peripheral device can generate an interrupt signal for a predetermined time interval following termination of an acknowledge signal.
摘要翻译：一种用于在包括处理单元和外围设备的计算系统中管理系统中断操作的装置。该装置包括用于发送影响外围设备和处理单元之间的操作连接的信号的传输电路; 用于产生与每个外围设备相关联的中断信号的中断驱动电路将传输电路从第一信号电平驱动到第二信号电平以产生中断信号; 以及用于由处理单元产生确认信号的确认驱动电路。每个应答驱动电路将传输电路从初始信号电平驱动到指示信号电平以产生确认信号，并且在确认信号终止时将传输电路从指示信号电平驱动到初始信号电平。在其优选实施例中，该装置规定，在确认信号终止之后，外围设备可以在预定时间间隔内产生中断信号。

2. 发明授权

US5388218A Apparatus and method for supporting a transfer trapping discipline for a non-enabled peripheral unit within a computing system 失效
标题翻译：用于支持计算系统内的非启用的外围单元的转移捕获规则的装置和方法
公开(公告)号：US5388218A
公开(公告)日：1995-02-07
申请号：US836647
申请日：1992-02-14
申请人： Douglas D. Gephardt , Andrew McBride
发明人： Douglas D. Gephardt , Andrew McBride
IPC分类号： G06F13/14 , G06F13/40 , G06F15/02
CPC分类号： G06F13/4068
摘要： An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled. The invention further comprises a method for managing communications within such a computing system comprising the steps of monitoring the enablement profile; generating a feedback signal representative of the enablement profile; communicating the feedback signal to the processing unit; and configuring the processing unit to respond to the feedback signal to determine whether to employ a transfer trapping discipline.
摘要翻译：一种用于管理包括处理单元和多个外围单元的计算系统内的通信的装置。所述处理单元从所述计算系统内的多个轨迹接收信息，并且根据预定标准响应于所述信息确定启用简档。处理单元响应启用简档以选择性地启用指定的外围单元。该装置包括用于监视启用简档的监视电路; 逻辑电路，用于逻辑地处理所述启用简档并生成表示所述启用简档的反馈信号; 以及用于将来自逻辑电路的反馈信号传送到处理单元的发送电路。处理单元响应于反馈信号以确定是否采用传送陷印规则，从而存储目的地为非启用的外围设备的传输，直到启用了非启用的单元。本发明还包括一种用于管理这种计算系统内的通信的方法，包括以下步骤：监视启用简档; 产生代表启用简档的反馈信号; 将所述反馈信号传送到所述处理单元; 以及配置所述处理单元以响应所述反馈信号以确定是否采用转移捕获规则。

3. 发明授权

US07043679B1 Piggybacking of ECC corrections behind loads 有权
标题翻译：搭载负载后的ECC校正
公开(公告)号：US07043679B1
公开(公告)日：2006-05-09
申请号：US10180207
申请日：2002-06-27
申请人： Chetana N. Keltcher , William Alexander Hughes , Andrew McBride
发明人： Chetana N. Keltcher , William Alexander Hughes , Andrew McBride
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G06F11/1064
摘要： An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.
摘要翻译：一种装置，包括被配置为检测和校正存储器中的第一数据的负载访问的非目标部分中的ECC错误的电路。 ECC错误检查电路被配置为响应于检测到第一数据的非目标第一部分中的错误而传达第一指示。微代码单元被耦合以接收ECC检查电路已经检测到ECC错误的第一指示，并且响应于指示分派由微代码单元存储的第一微代码例程。第一微代码例程包括指令，当被执行时，该指令校正第一部分中的ECC错误。纠正第一部分中的错误不包括取消与负载访问相对应的数据。

4. 发明申请

US20170114695A1 COMBINING MODEL AND DELTA PRESSURE BASED SOOT LOAD ESTIMATES 审中-公开
公开(公告)号：US20170114695A1
公开(公告)日：2017-04-27
申请号：US14924399
申请日：2015-10-27
申请人： Jordan Mosher , Nishant Singh , Andrew McBride
发明人： Jordan Mosher , Nishant Singh , Andrew McBride
IPC分类号： F01N11/00 , G01M15/10 , G01N15/06
CPC分类号： F01N11/00 , B01D46/44 , F01N2550/04 , F01N2900/1606 , G01M15/102 , Y02T10/47
摘要： A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.

5. 发明授权

US6076146A Cache holding register for delayed update of a cache line into an instruction cache 失效
标题翻译：缓存保持寄存器用于将高速缓存行的延迟更新延迟到指令高速缓存
公开(公告)号：US6076146A
公开(公告)日：2000-06-13
申请号：US310356
申请日：1999-05-12
申请人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
发明人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00 , G06F13/00
CPC分类号： G06F9/382 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.
摘要翻译：提供采用高速缓存保持寄存器的指令高速缓存器。当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。指令字节是从主存储器接收到的预解码的。如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。采用第二高速缓存保存寄存器来存储预取的高速缓存行。

6. 发明授权

US10392998B2 Combining model and delta pressure based soot load estimates 有权
公开(公告)号：US10392998B2
公开(公告)日：2019-08-27
申请号：US14924399
申请日：2015-10-27
申请人： Jordan Mosher , Nishant Singh , Andrew McBride
发明人： Jordan Mosher , Nishant Singh , Andrew McBride
IPC分类号： B01D46/44 , F01N11/00 , G01M15/10
摘要： A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.

7. 发明授权

US6049863A Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor 失效
标题翻译：用于指示超标量微处理器内可变字节长度指令中操作码字节位置的预编码技术
公开(公告)号：US6049863A
公开(公告)日：2000-04-11
申请号：US873344
申请日：1997-06-11
申请人： Thang M. Tran , Rammohan Narayan , Andrew McBride , Karthikeyan Muthusamy
发明人： Thang M. Tran , Rammohan Narayan , Andrew McBride , Karthikeyan Muthusamy
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3816 , G06F9/3853
摘要： A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three predecode bits associated with each byte of instruction code: a "start" bit, an "end" bit, and a "functional" bit. The start bit is set if the associated byte is the first byte of the instruction. Similarly, the end bit is set if the byte is the last byte of the instruction. The functional bits convey information regarding the location of an opcode byte for a particular instruction as well as an indication of whether the instruction can be decoded directly by the decode logic of the processor or whether the instruction is executed by invoking a microcode procedure controlled by an MROM unit. For fast path instructions, the functional bit is set for each prefix byte included in the instruction, and cleared for other bytes. For MROM instructions, the functional bit is cleared for each prefix byte and is set for other bytes. The type of instruction (either fast path or MROM) may thus be determined by examining the functional bit corresponding to the end byte of the instruction. If that functional bit is clear, the instruction is a fast path instruction. Conversely, if that functional bit is set, the instruction is an NMOM instruction. After an MROM instruction is identified, the functional bits for the instruction may be inverted. Subsequently, the opcode for both fast path and MROM instructions may readily be located (by the alignment logic) by determining the first byte within the instruction that has a cleared functional bit.
摘要翻译：预解码单元被配置为在可变字节长度指令被存储在超标量微处理器的指令高速缓存之前预先解码。预解码单元产生与指令代码的每个字节相关联的三个预解码位：“起始”位，“结束”位和“功能”位。如果相关字节是指令的第一个字节，则起始位置1。类似地，如果字节是指令的最后一个字节，则结束位置1。功能位传送关于特定指令的操作码字节的位置的信息以及指令是否可以由处理器的解码逻辑直接解码，或者指令是否通过调用由控制的微代码过程来执行 MROM单位。对于快速通道指令，为指令中包含的每个前缀字节设置功能位，并为其他字节清零。对于MROM指令，每个前缀字节清除功能位，并为其他字节设置。因此，可以通过检查对应于指令的结束字节的功能位来确定指令的类型（快速路径或MROM）。如果该功能位清零，该指令是快速路径指令。相反，如果该功能位被置位，则指令是NMOM指令。识别出MROM指令后，指令的功能位可能会反转。随后，快速路径和MROM指令的操作码可以通过确定具有清除的功能位的指令内的第一个字节来容易地（由对准逻辑）定位。

8. 发明授权

US6016545A Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor 失效
标题翻译：用于在高频微处理器中存储高速缓存线相关数据的减小尺寸的存储装置
公开(公告)号：US6016545A
公开(公告)日：2000-01-18
申请号：US991694
申请日：1997-12-16
申请人： Rupaka Mahalingaiah , Andrew McBride , Thang M. Tran
发明人： Rupaka Mahalingaiah , Andrew McBride , Thang M. Tran
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3844
摘要： A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of cache lines in the instruction cache. Each storage location in the storage is mappable to multiple cache lines, any one of which can be associated with the data stored in the storage location. The storage may thereby be smaller than a storage which provides an equal number of storage locations as the number of cache lines in the instruction cache. Access time to the storage may be reduced, therefore providing for a higher frequency implementation. Still further, semiconductor substrate area occupied by the storage may be decreased. In one embodiment, the storage is indexed by a subset of the index bits used to index the instruction cache. The subset comprises the least significant bits of the cache index. In other words, the cache lines which share a particular storage location within the storage differ in the most significant cache index bits. Therefore, code which exhibits spatial locality may experience little conflict for the storage locations.
摘要翻译：微处理器将包含比指令高速缓存中的高速缓存行的数量更少的存储位置的存储器中的高速缓存线相关数据（例如在所示实施例中的分支预测或预解码数据）存储在存储器中。存储器中的每个存储位置可映射到多个高速缓存行，其中任何一个可以与存储在存储位置中的数据相关联。因此，存储器可以小于提供与指令高速缓存中的高速缓存行数相同数量的存储位置的存储器。可能减少对存储器的访问时间，因此提供更高频率的实现。此外，可以减少由存储器占据的半导体衬底区域。在一个实施例中，存储器被用于索引指令高速缓存的索引位的子集索引。该子集包括高速缓存索引的最低有效位。换句话说，在存储器中共享特定存储位置的高速缓存行在最重要的高速缓存索引位中不同。因此，展示空间局部性的代码可能对存储位置的冲突很小。

9. 发明授权

US06349365B1 User-prioritized cache replacement 有权
标题翻译：用户优先级高速缓存替换
公开(公告)号：US06349365B1
公开(公告)日：2002-02-19
申请号：US09415892
申请日：1999-10-08
申请人： Andrew McBride
发明人： Andrew McBride
IPC分类号： G06F1200
CPC分类号： G06F12/126
摘要： A method and apparatus for encoding cache replacement priority information is disclosed. A computer software program may be used to allow programmers to specify which portions of source or object code being generated should be treated as high priority with respect to cache line replacement. The cache line replacement information may be encoded as special prefix bits/bytes, special opcodes, or as a separate data file. The software program may also be configured to autonomously determine which portions of the object code being generated should be identified as high priority with respect to cache line replacement. The program may also allow the programmer to specify certain points in the code after which instructions that had previously been identified as high priority should be reclassified as low priority. Opcodes or prefix bytes clearing previously stored cache replacement information may also be encoded in the object code. A microprocessor and computer system configured to execute code with embedded cache line replacement information are also disclosed.
摘要翻译：公开了一种用于编码高速缓存替换优先级信息的方法和装置。可以使用计算机软件程序来允许程序员指定所生成的源代码或目标代码的哪些部分应被视为关于高速缓存行替换的高优先级。高速缓存行替换信息可以被编码为特殊的前缀比特/字节，特殊的操作码，或作为单独的数据文件。软件程序还可以被配置为自主地确定正在生成的目标代码的哪些部分应被识别为关于高速缓存行替换的高优先级。该程序还可以允许程序员指定代码中的某些点，之后将先前被识别为高优先级的指令重新分类为低优先级。清除先前存储的高速缓存替换信息的操作码或前缀字节也可以被编码在目标代码中。还公开了一种被配置为执行具有嵌入式高速缓存行替换信息的代码的微处理器和计算机系统。

10. 发明授权

US06175909B1 Forwarding instruction byte blocks to parallel scanning units using instruction cache associated table storing scan block boundary information for faster alignment 有权
标题翻译：使用指令高速缓存关联表将存储扫描块边界信息的指令字节块转发到并行扫描单元，以便更快地对齐
公开(公告)号：US06175909B1
公开(公告)日：2001-01-16
申请号：US09243223
申请日：1999-02-02
申请人： Andrew McBride
发明人： Andrew McBride
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A microprocessor configured to use historical scan information to speed instruction scanning is disclosed. The microprocessor may comprise an instruction cache, a scanning history table, routing logic, and two or more scanning units. The instruction cache is configured to output sequences of stored instruction bytes in response to receiving corresponding fetch addresses. The scanning history table, which may also receive the fetch addresses, is configured to output corresponding stored scan block boundary information. The routing logic, which is coupled between the instruction cache, scanning history table, and scanning units, is configured to route the first N instructions to the first scanning unit, and the second N instructions to the second scanning unit, wherein N is a predetermined integer greater than one. The scanning units are configured to operate independently and in parallel. The scanning history information may be initially stored in the scanning history table by a predecode unit coupled between the instruction cache and a memory subsystem. Alternatively, the scanning units may scan the instructions in a traditional manner during a first access and then store the scan information in the scanning history table for subsequent accesses. The scan history information may be stored in the scan history table as scan block indicator bits or as byte counts associated with a particular fetch address. A computer system and method for scanning instructions are also disclosed.
摘要翻译：公开了一种被配置为使用历史扫描信息来加速指令扫描的微处理器。微处理器可以包括指令高速缓存，扫描历史表，路由逻辑和两个或更多个扫描单元。指令高速缓存被配置为响应于接收相应的获取地址而输出存储的指令字节的序列。还可以接收提取地址的扫描历史表被配置为输出相应的存储的扫描块边界信息。耦合在指令高速缓存，扫描历史表和扫描单元之间的路由逻辑被配置为将第一N个指令发送到第一扫描单元，并且将第二N个指令路由到第二扫描单元，其中N是预定的大于1的整数。扫描单元被配置为独立地并行地操作。可以通过耦合在指令高速缓存和存储器子系统之间的预解码单元将扫描历史信息最初存储在扫描历史表中。或者，扫描单元可以在第一次访问期间以传统方式扫描指令，然后将扫描信息存储在扫描历史表中用于后续访问。扫描历史信息可以作为扫描块指示符位存储在扫描历史表中，或作为与特定提取地址相关联的字节计数。还公开了一种用于扫描指令的计算机系统和方法。

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