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1. 发明授权

US5598539A Apparatus and method for achieving hot docking capabilities for a dockable computer system 失效
标题翻译：用于实现可停靠的计算机系统的热对接能力的装置和方法
公开(公告)号：US5598539A
公开(公告)日：1997-01-28
申请号：US553196
申请日：1995-11-07
申请人： Douglas D. Gephardt , Scott Swanstrom
发明人： Douglas D. Gephardt , Scott Swanstrom
IPC分类号： G06F13/14 , G06F1/16 , G06F3/00 , G06F13/364 , G06F13/40 , G06F13/20
CPC分类号： G06F1/1632 , G06F13/364 , G06F13/4031 , G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： A dockable computer system is capable of performing hot docking or warm docking. Hot docking refers to an ability to dock when the portable computer or docking station are running at full power. Warm docking refers to an ability to dock when the portable computer and docking station are running in a reduced power state. The dockable computer system employs a docking agent which is capable of quieting (rendering inactive) the buses of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal can be provided from software, a user-actuated switch, or an infrared signal. The docking agent preferably quiets the system bus by idling the system bus or asserting bus ownership or bus mastership over the system bus. The docking agent is able to assert bus ownership or bus mastership over the system bus. Alternatively, the docking agent can perform a software idle subroutine or an interrupt subroutine which idles the system bus. Preferably, the system bus is idled by disabling clock signals to it. Preferably, the docking agent also removes bus ownership requests, interrupt requests, and DMA requests from the station bus and system bus.
摘要翻译：可停放的计算机系统能够进行热对接或热对接。热对接是指当便携式计算机或坞站以全功率运行时停靠的能力。温暖对接是指当便携式计算机和对接站在降低功率状态下运行时停靠的能力。可停靠的计算机系统采用对接代理，其能够响应于通知信号而使便携式计算机和对接站的总线静音（使得无效）。通知信号表示状态从脱离状态到对接状态或从对接状态到解除停止状态的变化。通知信号可以由软件，用户驱动的开关或红外信号提供。对接代理优选地通过使系统总线空转或通过系统总线断言总线所有权或总线主管来对系统总线进行停顿。对接代理能够通过系统总线来显示总线所有权或总线主控权。或者，对接代理可以执行软件空闲子程序或空闲系统总线的中断子程序。优选地，系统总线通过禁止其时钟信号而空转。优选地，对接代理还从站总线和系统总线去除总线所有权请求，中断请求和DMA请求。

2. 发明授权

US5668977A Dockable computer system capable of electric and electromagnetic communication 失效
标题翻译：可进行电力和电磁通信的可移动计算机系统
公开(公告)号：US5668977A
公开(公告)日：1997-09-16
申请号：US642188
申请日：1996-05-06
申请人： Scott Swanstrom , Douglas D. Gephardt
发明人： Scott Swanstrom , Douglas D. Gephardt
IPC分类号： G06F1/16 , G06F3/00 , G06F13/00 , G06F13/14 , G06F13/40 , G06F15/177
CPC分类号： G06F13/4081 , G06F1/1632
摘要： A dockable computer system includes a portable computer (notebook or laptop) and a docking station (base unit). The portable computer and docking station both include a communication system so that messages can be communicated when the docking station is in an undocked state preparatory to a docked state. The communication system is preferably an infrared communication system. A communication protocol is also provided for generating an advance notice signal to warn of an impending dock. The communication protocol includes a CONNECT message, a CONNECT DETECTED message, and a CONFIRM message. Preferably, the CONNECT message is sent at a non-standard AT/PC baud rate. The communication system allows the dockable computer system to advantageously generate an advance notice signal of an impending dock and to transfer parameters necessary for the employment of sophisticated protective measures which protect the active buses of the portable computer and docking station during a docking event. Preferably, the portable computer performs an interrupt subroutine in response to receiving the CONNECT message. The notice signal is generated as part of the interrupt subroutine.
摘要翻译：可停放的计算机系统包括便携式计算机（笔记本或笔记本电脑）和对接站（基本单元）。便携式计算机和对接站都包括通信系统，使得当对接站处于准备停靠状态的解除停靠状态时可以传送消息。通信系统优选地是红外通信系统。还提供通信协议用于产生提前通知信号以警告即将到来的码头。通信协议包括CONNECT消息，CONNECT DETECTED消息和CONFIRM消息。优选地，以非标准AT / PC波特率发送CONNECT消息。通信系统允许可停靠的计算机系统有利地生成即将到来的码头的预告信号，并且传送在对接事件期间保护便携式计算机和对接站的有源总线的复杂保护措施所必需的参数。优选地，便携式计算机响应于接收到CONNECT消息而执行中断子程序。通知信号是作为中断子程序的一部分生成的。

3. 发明授权

US5632020A System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking 失效
标题翻译：用于将便携式计算机对接到主计算机的系统，而不会在对接代理中暂停处理器操作，从而驱动总线在停靠期间无效
公开(公告)号：US5632020A
公开(公告)日：1997-05-20
申请号：US255663
申请日：1994-06-09
申请人： Douglas D. Gephardt , Scott Swanstrom
发明人： Douglas D. Gephardt , Scott Swanstrom
IPC分类号： G06F3/00 , G06F1/16 , G06F13/14 , G06F13/362 , G06F13/364 , G06F13/38 , G06F13/40 , G06F13/20 , G06F13/36
CPC分类号： G06F13/4081 , G06F1/1632 , G06F13/364 , G06F13/4031
摘要： A computer system includes a bus arbiter for providing immediate access to a bus in response to an external requirement or event. In a dockable computer system capable of hot docking or warm docking, the bus arbiter grants exclusive, non-preemptive access to the buses to the docking agent which is capable of quieting (rendering inactive) the bus of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch, or an infrared signal. In an audio-capable computer, the bus arbiter provides exclusive non-preemptive access to the digital signal processing peripheral device so that audio glitches are avoided. The arbiter preferably includes an override circuit for countermanding the fairness scheme employed by the bus arbiter and granting immediate bus access in response to the external event or condition. The bus arbiter preferably is able to provide fixed or rotating priority for bus accesses of other peripheral devices on the bus. The arbiter is preferably integrated with the main processor of the computer system.
摘要翻译：计算机系统包括总线仲裁器，用于响应于外部要求或事件提供对总线的即时访问。在能够进行热对接或热对接的可停靠的计算机系统中，总线仲裁器向对接代理授予对总线的独占的非抢占性访问，该对接代理能够响应于便携式计算机和对接站的总线（呈现无效）到一个通知信号。通知信号表示状态从脱离状态到对接状态或从对接状态到解除停止状态的变化。通知信号可以由软件，用户驱动的开关或红外信号提供。在音频计算机中，总线仲裁器提供对数字信号处理外围设备的独占非抢占式访问，从而避免了音频毛刺。仲裁器优选地包括用于对抗总线仲裁器采用的公平方案并且响应于外部事件或状况授权立即总线访问的超控电路。总线仲裁器优选地能够为总线上的其他外围设备的总线访问提供固定或旋转优先级。仲裁器最好与计算机系统的主处理器集成。

4. 发明授权

US5598537A Apparatus and method for driving a bus to a docking safe state in a dockable computer system including a docking station and a portable computer 失效
标题翻译：一种用于在包括对接站和便携式计算机的可对接计算机系统中将总线驱动到对接安全状态的装置和方法
公开(公告)号：US5598537A
公开(公告)日：1997-01-28
申请号：US280314
申请日：1994-07-26
申请人： Scott Swanstrom , Douglas D. Gephardt
发明人： Scott Swanstrom , Douglas D. Gephardt
IPC分类号： G06F1/18 , G06F1/16 , G06F3/00 , G06F13/364 , G06F13/40 , H05K7/10 , G06F13/00
CPC分类号： G06F1/1632 , G06F13/364 , G06F13/4036 , G06F13/4072 , G06F13/4081
摘要： In a dockable computer system capable of hot docking or warm docking, a docking safe circuit drives the bus of the portable computer and docking station to a docking safe state in response to a DOCK signal. The DOCK signal may be a notice signal indicative of a change of state from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch or an infrared signal. Preferably, the docking safe state or dockable state is a state in which: the ground conductors of the buses are referenced to a common ground potential; the buses are "quiet" or non-transitioning; the bidirectional terminals on the bus of the portable computer are set to an output state; the bidirectional terminals of the bus of the docking station are set to an input state; and the signaling levels of the buses have the same voltage potential. Preferably, the present invention is implemented on a peripheral component interconnect (PCI) bus.
摘要翻译：在能够热对接或热对接的可停靠的计算机系统中，对接安全电路响应于DOCK信号将便携式计算机和坞站的总线驱动到对接安全状态。 DOCK信号可以是指示状态从脱离状态到对接状态或从停靠状态到解除停止状态的通知信号。通知信号可以由软件，用户致动的开关或红外信号提供。优选地，对接安全状态或可停靠状态是这样的状态，其中：总线的接地导体参考公共地电位; 公共汽车是“安静的”还是非转型的; 便携式计算机总线上的双向终端设置为输出状态; 对接站的总线的双向端子被设置为输入状态; 并且总线的信号电平具有相同的电压电位。优选地，本发明在外围组件互连（PCI）总线上实现。

5. 发明授权

US5822568A System for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller 失效
公开(公告)号：US5822568A
公开(公告)日：1998-10-13
申请号：US650571
申请日：1996-05-20
申请人： Scott Swanstrom
发明人： Scott Swanstrom
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprising an improved DMA controller for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises one or more buses for transferring data. A CPU, system memory and a plurality of peripheral devices are interconnected by the buses. Each of the peripheral devices comprises one or more peripheral interrupt request outputs. The system further comprises a programmable DMA controller coupled to the bus which receives the peripheral interrupt request outputs. The DMA controller is configured to perform a DMA transfer on the one or more buses between two or more devices, including the system memory and the plurality of peripheral devices. The CPU programs the DMA controller to start the DMA transfer in response to one of the plurality of peripheral devices generating an interrupt request on its interrupt request output or to start the DMA transfer immediately. The system further comprises a peripheral interrupt controller (PIC) coupled to the CPU. The PIC includes a plurality of PIC interrupt request inputs coupled to the DMA controller. The DMA controller is configured to selectively couple the peripheral interrupt request outputs from the peripheral devices to the plurality of PIC interrupt request inputs of the PIC, to selectively decouple the peripheral interrupt request outputs from the peripheral devices from the plurality of PIC interrupt request inputs of the PIC, and to selectively generate a plurality of interrupt requests on the plurality of PIC interrupt request inputs of the PIC when the peripheral interrupt request outputs from the peripheral devices are decoupled from the plurality of PIC interrupt request inputs. Thus, the DMA controller renders the CPU more responsive to real-time events by servicing a portion of the peripheral interrupts.

6. 发明授权

US5872942A Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent byte slicing 失效
标题翻译：具有多媒体总线的计算机系统，包括执行智能字节分片的集中式I / O处理器
公开(公告)号：US5872942A
公开(公告)日：1999-02-16
申请号：US926729
申请日：1997-09-10
申请人： Scott Swanstrom , Steven L. Belt
发明人： Scott Swanstrom , Steven L. Belt
IPC分类号： G06F13/12 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N21/238 , G06F13/38
CPC分类号： H04N21/238 , G06F13/124 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/4013 , G06F13/4022 , G06F13/4027
摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
摘要翻译：针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。该系统包括标准本地系统总线或扩展总线，如PCI总线，还包括一个专用的实时总线或多媒体总线。各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。因此，字节分片多媒体总线允许不同的外设同时共享总线。因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

7. 发明授权

US5754801A Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent data transfers 失效
标题翻译：具有多媒体总线的计算机系统，并且包括执行智能数据传输的集中式I / O处理器
公开(公告)号：US5754801A
公开(公告)日：1998-05-19
申请号：US650938
申请日：1996-05-17
申请人： Andy Lambrecht , Scott Swanstrom , Drew Dutton
发明人： Andy Lambrecht , Scott Swanstrom , Drew Dutton
IPC分类号： G06F13/12 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N21/238 , H04N7/173 , G06F3/14 , G06F17/00
CPC分类号： G06F13/36 , G06F13/124 , G06F13/368 , G06F13/372 , G06F13/4022 , G06F13/4027 , H04N21/238
摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for the multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
摘要翻译：针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。该系统包括标准本地系统总线或扩展总线，如PCI总线，还包括一个专用的实时总线或多媒体总线。各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的专用或集中式I / O处理器，其操作以通过系统引导或引导流信息。集中式I / O处理器包括用于存储用于多媒体设备的数据速率，数据周期，数据源和数据目的地信息的存储器。因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

8. 发明授权

US5920891A Architecture and method for controlling a cache memory 失效
标题翻译：用于控制高速缓冲存储器的体系结构和方法
公开(公告)号：US5920891A
公开(公告)日：1999-07-06
申请号：US650523
申请日：1996-05-20
申请人： Andy Steinbach , Scott Swanstrom , Michael Wisor
发明人： Andy Steinbach , Scott Swanstrom , Michael Wisor
IPC分类号： G06F12/08 , G06F13/14 , G06F13/38
CPC分类号： G06F12/0835
摘要： A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.
摘要翻译：一种高速缓冲存储器系统，包括用于连接到总线主机的第一总线和用于连接到系统存储器的第二总线。系统存储器包括多个可高速缓存的存储器位置。总线桥提供第一总线和第二总线之间的接口。用于缓存存储在可高速缓存存储单元中的数据的高速缓冲存储器控制器被连接到系统存储器。高速缓存存储器控制器包括直接耦合到第一总线的监听控制电路，用于在第一总线上窥探总线事务，并且进一步耦合到第二总线，用于在所述第二总线上窥探总线事务。

9. 发明授权

US5754884A Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller 失效
标题翻译：用于改善使用中断服务DMA控制器的个人计算机的实时功能的方法
公开(公告)号：US5754884A
公开(公告)日：1998-05-19
申请号：US650524
申请日：1996-05-20
申请人： Scott Swanstrom
发明人： Scott Swanstrom
IPC分类号： G06F13/28 , G06F13/00 , G06F13/38
CPC分类号： G06F13/28
摘要： A method for performing data transfers in a computer system comprising an improved DMA controller (DMAC) for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises a CPU, system memory, the DMA controller and a plurality of peripheral devices interconnected by buses. The CPU programs the peripheral, such as a disk drive, to retrieve or store data. When the peripheral has retrieved the data or is ready to receive the data the peripheral generates an interrupt. The CPU programs the DMAC to perform DMA transfers between the peripheral and the system memory and to selectively decouple the interrupt request from the peripheral to the CPU so that the DMAC can service the interrupt from the peripheral rather than the CPU. The decoupling is selectively performed so that, in the case of a write to the peripheral, the DMAC can receive the interrupt from the peripheral and perform the data transfer. In the case of a read from the peripheral, the DMAC performs the data transfer, then receives and services the interrupt from the peripheral. The CPU also programs the DMAC to selectively generate an interrupt to the CPU upon completion of DMA transfers. The CPU also programs the DMAC to selectively wait for an interrupt from the peripheral before performing the DMA transfers. The CPU also programs the DMAC to selectively poll for status in the peripheral and check for error conditions.
摘要翻译：一种用于在计算机系统中执行数据传输的方法，包括改进的DMA控制器（DMAC），用于在外围设备和系统存储器之间执行DMA传输，以及接收和维护由外围设备产生的中断。该系统包括CPU，系统存储器，DMA控制器和由总线互连的多个外围设备。 CPU对外围设备（如磁盘驱动器）进行编程，以检索或存储数据。当外设检索到数据或准备好接收数据时，外设会产生中断。 CPU对DMAC进行编程，以在外设和系统存储器之间执行DMA传输，并选择性地将外设与CPU中断请求分离，以使DMAC可以从外设而不是CPU来服务中断。选择性地执行去耦，使得在对外设的写入的情况下，DMAC可以从外设接收中断并执行数据传输。在从外围设备读取的情况下，DMAC执行数据传输，然后从外设接收和服务中断。在DMA传输完成后，CPU还对DMAC进行编程以选择性地向CPU产生中断。在执行DMA传输之前，CPU还对DMAC进行编程，以选择性地等待来自外设的中断。 CPU还可以对DMAC进行编程，以选择轮询外设中的状态并检查错误状况。

10. 发明授权

US5964859A Allocatable post and prefetch buffers for bus bridges 失效
标题翻译：总线桥可分配的后置缓冲区和预取缓冲区
公开(公告)号：US5964859A
公开(公告)日：1999-10-12
申请号：US960819
申请日：1997-10-30
申请人： Andy Steinbach , Scott Swanstrom , Michael Wisor
发明人： Andy Steinbach , Scott Swanstrom , Michael Wisor
IPC分类号： G06F13/40 , G06F13/14
CPC分类号： G06F13/4059
摘要： A computing system and bus bridge in which the bus bridge includes a buffer pool wherein the storage buffers contained in the buffer pool may be allocated as post buffers or fetch buffers in response to appropriate requests from the bus bridge. In the preferred embodiment, the bus bridge includes a buffer pool control unit adapted to temporarily allocate any of the plurality of storage buffers as either a post buffer or a fetch buffer depending upon the system requirements. Broadly speaking, the present invention contemplates a computing system including a first component connected to a first bus, a second component connected to a second bus, and a bus bridge connected to a first and second busses. The bus bridge includes a buffer pool comprised of a plurality of storage buffers and a buffer pool control unit that is capable of temporarily allocating at least one of the storage buffers as either a post buffer or a fetch buffer in response to system requirement. Preferably, each storage buffer includes corresponding tag information for identifying an origin or destination location within a main memory of the data associated with the storage buffer. In one embodiment, each of the plurality of storage buffers includes corresponding allocation information used by the buffer pool control unit for the temporary allocation of the storage buffers. In a presently preferred embodiment, the allocation information includes an available bit indicative of whether the storage buffers available for allocation and a post/fetch bit indicative of whether an unavailable storage buffer is currently allocated as a post buffer or as a fetch buffer. The allocation information is accessible by the buffer pool control unit and is used by the buffer pool control unit for temporarily allocating the storage buffers.
摘要翻译：一种计算系统和总线桥，其中总线桥包括缓冲池，其中响应于来自总线桥的适当请求，缓冲池中包含的存储缓冲器可以被分配为后缓冲器或提取缓冲器。在优选实施例中，总线桥接器包括缓冲池控制单元，其适于根据系统要求将多个存储缓冲器中的任何一个临时分配为后缓冲器或提取缓冲器。广义而言，本发明考虑了一种包括连接到第一总线的第一组件，连接到第二总线的第二组件和连接到第一和第二总线的总线桥的计算系统。总线桥包括由多个存储缓冲器组成的缓冲池和缓冲池控制单元，该缓冲池控制单元能够响应于系统要求将至少一个存储缓冲器分配为后缓冲器或提取缓冲器。优选地，每个存储缓冲器包括用于标识与存储缓冲器相关联的数据的主存储器内的原始位置或目的地位置的相应标签信息。在一个实施例中，多个存储缓冲器中的每一个包括由缓冲池控制单元用于临时分配存储缓冲器的相应分配信息。在当前优选实施例中，分配信息包括指示可用于分配的存储缓冲器的可用位以及指示当前是否将不可用存储缓冲器分配为后缓冲器或作为读取缓冲器的后/取位。分配信息可由缓冲池控制单元访问，并由缓冲池控制单元用于临时分配存储缓冲区。

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