专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06357024B1 Electronic system and method for implementing functional redundancy checking by comparing signatures having relatively small numbers of signals 有权
标题翻译：用于通过比较具有相对较少数量的信号的签名来实现功能冗余校验的电子系统和方法
公开(公告)号：US06357024B1
公开(公告)日：2002-03-12
申请号：US09132334
申请日：1998-08-12
申请人： Drew J. Dutton , Dan S. Mudgett , Scott A. White
发明人： Drew J. Dutton , Dan S. Mudgett , Scott A. White
IPC分类号： G06F1100
CPC分类号： G06F11/1654 , G06F11/1641 , G06F11/165 , G06F2201/83
摘要： An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are “point-to-point”, enabling the processor buses to achieve relatively high data transfer rates.
摘要翻译：通过比较由两个不同的电子设备（例如中央处理单元（CPU））产生的“签名”来呈现用于实现功能冗余检查（FRC）的电子系统和方法。签名包括反映每个CPU的内部状态的相对较少数量的信号。该电子系统包括第一和第二CPU。每个CPU配置为执行指令并产生输出信号。第一和第二CPU优选地是相同的并且同时执行指令，使得它们的内部状态和产生的输出信号在任何给定的时间应该相同。每个CPU包括用于生成签名的签名生成器。电子系统还包括耦合以接收签名的比较单元。比较单元比较签名并且如果签名不相同则产生错误信号。电子系统可以是计算机系统，还包括系统总线和芯片组逻辑。系统总线适于耦合到一个或多个外围设备。芯片组逻辑耦合在第一和第二CPU与系统总线之间，并且用作第一和第二CPU与系统总线之间的接口。第一和第二CPU通过单独的处理器总线耦合到芯片组逻辑。单独处理器总线的信号线的至少一部分是“点到点”，使得处理器总线能够实现相对较高的数据传输速率。

2. 发明授权

US5099140A Synchronous clock source selector 失效
标题翻译：同步时钟源选择器
公开(公告)号：US5099140A
公开(公告)日：1992-03-24
申请号：US575594
申请日：1990-08-31
申请人： Dan S. Mudgett
发明人： Dan S. Mudgett
IPC分类号： G06F1/08 , H03K5/13 , H03K5/26
CPC分类号： G06F1/08 , H03K5/13 , H03K5/26
摘要： A clock source selector provides at least one set of clock signals selected from a plurality of clock sources and a synchronized transition from an old clock source to a new clock source. The clock source selector includes a gate having an output for providing the clock signals, a selector coupled between the plurality of clock sources and the gate for providing the gate with clock signals from selected ones of the clock sources responsive to selection signals, a detector for detecting a change in the selection signals from an old clock source to a new clock source, and a synchronizing circuit responsive to the detector for disabling the gate in synchronism with the old clock source and thereafter enabling the gate in synchronism with the new clock source.
摘要翻译：时钟源选择器提供从多个时钟源中选择的至少一组时钟信号和从旧时钟源到新时钟源的同步转换。时钟源选择器包括具有用于提供时钟信号的输出端的栅极，耦合在多个时钟源和栅极之间的选择器，用于响应于选择信号向所选择的时钟源提供来自选择的时钟源的时钟信号; 检测从旧时钟源到新时钟源的选择信号的变化，以及响应于检测器的同步电路，用于与旧时钟源同步地禁用门，此后使得门能够与新的时钟源同步。

3. 发明授权

US06775749B1 System and method for performing a speculative cache fill 失效
标题翻译：用于执行推测缓存填充的系统和方法
公开(公告)号：US06775749B1
公开(公告)日：2004-08-10
申请号：US10059934
申请日：2002-01-29
申请人： Dan S. Mudgett , Mark T. Fox
发明人： Dan S. Mudgett , Mark T. Fox
IPC分类号： G06F1316
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.
摘要翻译：计算机系统可以包括几个高速缓存，每个缓存被耦合以从共享存储器接收数据。高速缓存一致性机制可以被配置为接收缓存填充请求，并且作为响应，发送探测以确定其他高速缓存中是否包含所请求数据的副本。在发送探测器之后的某个时间，缓存控制器可以向请求设备提供对缓存填充请求的推测响应。通过在发送探针之后延迟提供推测性响应，可能会及时收到对探针的响应以验证推测性响应。

4. 发明授权

US5894578A System and method for using random access memory in a programmable interrupt controller 失效
标题翻译：在可编程中断控制器中使用随机存取存储器的系统和方法
公开(公告)号：US5894578A
公开(公告)日：1999-04-13
申请号：US575685
申请日：1995-12-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.
摘要翻译：提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。可编程中断控制器包括中断请求接口，中央中断控制器，随机存取存储器和至少一个处理器接口。中央中断控制器系统地从中断请求接口中选择中断请求。与每个中断请求相关联的信息存储在随机存取存储器中。中央中断控制器访问随机存取存储器中的信息，并使用当前选择的中断请求的信息和状态来确定当前选择的中断请求的下一状态。该信息被传递到处理器接口，以确定中断请求何时以及是否向其中一个CPU发布。

5. 发明授权

US5892956A Serial bus for transmitting interrupt information in a multiprocessing system 失效
标题翻译：用于在多处理系统中传输中断信息的串行总线
公开(公告)号：US5892956A
公开(公告)日：1999-04-06
申请号：US934261
申请日：1997-09-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F9/46 , G06F13/26
CPC分类号： G06F13/26
摘要： A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line to drive all the interrupt information to all the processors and a clock line to synchronize edges for the data stream. A third line, normally tri-stated, may be used to provide a parity error indication for the serial bus. The serial data includes a processor identification, a pin identification and state information. As the programmable interrupt controller sends the interrupt data on the serial bus, all the processors clock the data and check parity. If a processor finds a parity error, it drives the parity error indication low so that the information may be transmitted again. No processor will execute the command contained in the serial message before the time has elapsed for any of the processors to report a parity error. If there is no parity error, the processor accepts and decodes the message and asserts or deasserts the appropriate signal.
摘要翻译：一种用于多处理环境的可编程中断控制器，可以支持串行总线向处理器发送中断信息。中断串行总线具有数据线，用于将所有中断信息驱动到所有处理器和时钟线以同步数据流的边沿。通常三通道的第三行可用于为串行总线提供奇偶校验错误指示。串行数据包括处理器标识，引脚标识和状态信息。由于可编程中断控制器在串行总线上发送中断数据，所有的处理器都会对数据进行计时并检查奇偶校验。如果处理器发现奇偶校验错误，则将奇偶校验错误指示值驱动为低，以便再次发送信息。没有处理器将在任何处理器报告奇偶校验错误的时间过去之前执行包含在串行消息中的命令。如果没有奇偶校验错误，则处理器接受并解码消息，并声明或取消对相应信号的声明。

6. 发明授权

US5655142A High performance derived local bus and computer system employing the same 失效
标题翻译：高性能派生本地总线和采用相同的计算机系统
公开(公告)号：US5655142A
公开(公告)日：1997-08-05
申请号：US705884
申请日：1996-08-28
申请人： Douglas D. Gephardt , Dan S. Mudgett
发明人： Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F13/38 , G06F13/42 , G06F15/78 , G06F13/24
CPC分类号： G06F13/4217 , G06F13/423 , G06F15/7832
摘要： An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus. A latch is coupled to the multiplexed address/data (A/D) lines of the PCI bus and includes a set of output lines coupled to the address input lines of the externally connected peripheral device. The external latch is latched by the loading signal. The cycle definition signals of the PCI bus are further latched within the external latch to provide memory/IO and read/write signals to the external peripheral device. The data lines of the peripheral device may be connected directly to the multiplexed address/data lines of the PCI bus.
摘要翻译：提供了一种集成处理器，其包括CPU核心，耦合到CPU核心的本地总线以及耦合到本地总线的诸如存储器控制器，直接存储器访问控制器和中断控制器的各种外设。还提供总线接口单元以在CPU本地总线和PCI标准复用的外围总线之间进行接口。 CPU核心，存储器控制器，直接存储器访问控制器，中断控制器和总线接口单元都被并入公共集成电路芯片。还提供了本地总线控制单元，其能够与在PCI总线上执行的某些总线周期同步地产生加载信号和地址选通信号。本地总线控制单元允许通过PCI总线连接与CPU本地总线协议兼容的外部外设。锁存器耦合到PCI总线的复用的地址/数据（A / D）线，并且包括耦合到外部连接的外围设备的地址输入线的一组输出线。外部锁存器被加载信号锁存。 PCI总线的周期定义信号进一步锁存在外部锁存器内，以向外部外围设备提供存储/ IO和读/写信号。外围设备的数据线可以直接连接到PCI总线的复用地址/数据线。

7. 发明授权

US5557757A High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效
标题翻译：高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
公开(公告)号：US5557757A
公开(公告)日：1996-09-17
申请号：US190647
申请日：1994-02-02
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , G06F13/4027
摘要： An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
摘要翻译：集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚总线上的集成处理器。辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。不需要用于辅助总线的集成处理器的独立地址和数据线。因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。

8. 发明授权

US06976204B1 Circuit and method for correcting erroneous data in memory for pipelined reads 有权
标题翻译：用于校正用于流水线读取的存储器中的错误数据的电路和方法
公开(公告)号：US06976204B1
公开(公告)日：2005-12-13
申请号：US09882417
申请日：2001-06-15
申请人： Eric G. Chambers , James R. Magro , Dan S. Mudgett
发明人： Eric G. Chambers , James R. Magro , Dan S. Mudgett
IPC分类号： G11C7/10 , G11C29/00 , H03M13/00
CPC分类号： G11C7/1039 , G06F11/106 , G11C7/1006
摘要： A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.
摘要翻译：一种用于校正用于流水线读取的存储器中的错误数据的电路和方法。存储器控制器包括控制单元，存储单元和错误检测和校正单元。控制单元被配置为响应于存储器读取请求从存储器子系统读取包括相关联的纠错码的数据。错误检测和校正单元被耦合以接收数据并被配置为基于相关联的纠错码来确定该数据中是否存在错误。控制单元被配置为在存储单元中存储与存储器读取请求相对应的数据是错误的指示。控制单元还被配置为检测存储单元中的指示并且响应地执行来自存储器子系统的数据的后续读取并将该数据的校正版本写回到存储器子系统。

9. 发明授权

US5778431A System and apparatus for partially flushing cache memory 失效
标题翻译：用于部分刷新缓存的系统和设备
公开(公告)号：US5778431A
公开(公告)日：1998-07-07
申请号：US575684
申请日：1995-12-19
申请人： Saba Rahman , Dan S. Mudgett , Victor F. Andrade
发明人： Saba Rahman , Dan S. Mudgett , Victor F. Andrade
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0891 , G06F12/0835 , G06F2212/2146
摘要： A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode. As yet another alternative, the present invention can be implemented by comparing each memory window address value with the stored tag address in the cache.
摘要翻译：公开了一种计算机系统，用于响应于诸如外部存储器设备的系统资源的移除，修改或禁用而选择性地使高速缓冲存储器的内容无效。计算机系统包括界定单元，该接口单元为特定系统资源定义地址窗口。地址窗口是通过使用下位地址寄存器和高地址寄存器来实现的，它们是响应于较低和较高使能地址信号加载的。上位比较器将每个标签地址与上位地址寄存器值进行比较，下位比较器将每个标签地址与较低的地址寄存器值进行比较。如果标签地址落在窗口内，则会通过生成适当的控制信号来刷新。在替代实施例中，本发明可以通过微代码中的指令通过软件实现。作为另一替代方案，可以通过将每个存储器窗口地址值与高速缓存中存储的标签地址进行比较来实现本发明。

10. 发明授权

US5682310A Computer system including in-circuit emulation mode for debugging system management software 失效
标题翻译：计算机系统包括用于调试系统管理软件的在线仿真模式
公开(公告)号：US5682310A
公开(公告)日：1997-10-28
申请号：US602680
申请日：1996-02-16
申请人： Michael D. Pedneau , Hans Magnusson , Dan S. Mudgett
发明人： Michael D. Pedneau , Hans Magnusson , Dan S. Mudgett
IPC分类号： G06F11/28 , G06F11/22 , G06F11/36 , G06F9/44 , G06F11/00
CPC分类号： G06F11/3648
摘要： A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a "normal" memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code. If the SMM interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit again causes assertion of the ICE interrupt signal. The microprocessor core responsively requests the ICE vector and, the interrupt control unit causes the memory control unit to translate the requested address to a second memory location of the system memory at which an SMM vector is stored. The computer system allows an in-circuit emulation mode to be entered while the microprocessor core is executing out of the system management space by asserting the debug interrupt signal.
摘要翻译：提供了一种计算机系统，其包括具有ICE中断线的微处理器核，以支持计算机系统的在线仿真模式。耦合到微处理器核心的ICE中断线的中断控制单元根据外部“调试”中断信号和外部SMM（系统管理模式）中断信号的断言来控制存储器控制单元。在正常操作期间，微处理器核心从耦合到存储器控制单元的系统存储器的“正常”存储器区域执行代码。如果在微处理器内核工作在正常模式下调试中断信号被置位，则中断控制单元响应地将ICE中断信号置为微处理器内核，使微处理器内核从系统存储器读取ICE向量，然后执行ICE 码。如果在微处理器内核工作在正常模式时SMM中断信号被置位，则中断控制单元再次导致ICE中断信号的置位。微处理器核心响应地请求ICE向量，并且中断控制单元使存储器控制单元将请求的地址转换到存储SMM向量的系统存储器的第二存储器位置。计算机系统允许在微处理器核心通过断言调试中断信号执行系统管理空间之前进入在线仿真模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式