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11. 发明授权

US5561821A System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus 失效
标题翻译：通过分别在本地总线上驱动DMA配置寄存器的地址和存储地址来执行I / O访问和存储器访问的系统
公开(公告)号：US5561821A
公开(公告)日：1996-10-01
申请号：US145375
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.
摘要翻译：提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。

12. 发明授权

US5561819A Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller 失效
标题翻译：计算机系统在通过在DMA控制器中驱动本地总线上的范围内的地址来禁用非参与的外设的I / O寻址技术期间选择外围设备的字节通道
公开(公告)号：US5561819A
公开(公告)日：1996-10-01
申请号：US145376
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36 , G06F13/40
CPC分类号： G06F13/28 , G06F13/4018
摘要： A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.
摘要翻译：直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。外围设备响应地在指定的字节通道处接收或提供数据。结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。

13. 发明授权

US06173395B2 Mechanism to determine actual code execution flow in a computer 有权
标题翻译：确定计算机中实际代码执行流程的机制
公开(公告)号：US06173395B2
公开(公告)日：2001-01-09
申请号：US09135493
申请日：1998-08-17
申请人： Michael Wisor , Travis Wheatley , Dan S. Mudgett
发明人： Michael Wisor , Travis Wheatley , Dan S. Mudgett
IPC分类号： G06F1500
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3648
摘要： A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined. The bitmap entry contains a series of bits, each of which can indicate whether a conditional branch was taken, so that a single bitmap entry can represent a series of conditional branches.
摘要翻译：一种用于使用在执行某些指令时生成的跟踪数据来确定被测计算机中的指令执行顺序的方法和系统。在一个实施例中，该方法包括将轨迹数据中的初始条目定位并以由初始条目指示的指令开始以程序顺序扫描指令。当遇到分支指令时，检查跟踪数据以确定随后执行的指令。如果分支是无条件的，则跟踪数据中的相应地址条目指示下一条指令的地址。如果分支是有条件的，则跟踪数据中的相应位图条目包含一个指示分支是否被采取的位。从该位和指令本身，确定下一条指令。位图条目包含一系列位，每个位可以指示是否采用条件分支，以便单个位图条目可以表示一系列条件分支。

14. 发明授权

US5905898A Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效
标题翻译：基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
IPC分类号： G06F13/26 , G06F15/17 , G06F3/00
CPC分类号： G06F13/26 , G06F15/17
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译：提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。用于引用中断请求的中断请求标识代码按其优先顺序存储。每个嵌套缓冲区只需要等于优先级数量的条目数。

15. 发明授权

US5894577A Interrupt controller with external in-service indication for power management within a computer system 失效
标题翻译：具有外部在线指示的中断控制器，用于计算机系统内的电源管理
公开(公告)号：US5894577A
公开(公告)日：1999-04-13
申请号：US125336
申请日：1993-09-22
申请人： James R MacDonald , Douglas D. Gephardt , Dan S. Mudgett
发明人： James R MacDonald , Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F1/04 , G06F1/32 , G06F9/48 , G06F13/24 , G06F13/26 , G06F9/46
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译：中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。提供在线寄存器用于存储由微处理器服务的任何请求线的标识。在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

16. 发明授权

US5850558A System and method for referencing interrupt request information in a programmable interrupt controller 失效
标题翻译：用于在可编程中断控制器中引用中断请求信息的系统和方法
公开(公告)号：US5850558A
公开(公告)日：1998-12-15
申请号：US575664
申请日：1995-12-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.
摘要翻译：提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。每个中断请求都分配唯一的中断识别码，用于引用与每个中断请求相关联的存储设备中的信息。中断请求接口使用唯一的中断标识码来访问每个中断请求的信息，并确定中断请求是否应继续到其中一个处理器接口。处理器接口使用唯一的中断识别码来访问信息，以确定中断请求是否和何时发送给其中一个CPU。

17. 发明授权

US5850555A System and method for validating interrupts before presentation to a CPU 失效
标题翻译：在呈现给CPU之前验证中断的系统和方法
公开(公告)号：US5850555A
公开(公告)日：1998-12-15
申请号：US575683
申请日：1995-12-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F13/24 , G06F13/00 , G06F13/14
CPC分类号： G06F13/24
摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.
摘要翻译：提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。可编程中断控制器包括中断请求接口，有效性检查器和至少一个处理器接口。有效性检查器通过中断控制器来处理每个中断请求的状态。如果中断请求无效，则中断请求被取消。或者，如果中断请求在CPU响应后变为无效，则可编程中断控制器发出伪中断向量。

18. 发明授权

US5765003A Interrupt controller optimized for power management in a computer system or subsystem 失效
标题翻译：针对计算机系统或子系统中的电源管理优化的中断控制器
公开(公告)号：US5765003A
公开(公告)日：1998-06-09
申请号：US671831
申请日：1996-10-09
申请人： James R. MacDonald , Douglas D. Gephardt , Dan S. Mudgett
发明人： James R. MacDonald , Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F1/04 , G06F1/32 , G06F9/48 , G06F13/24 , G06F13/26
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译：中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。提供在线寄存器用于存储由微处理器服务的任何请求线的标识。在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

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