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1. 发明授权

US06247146B1 Method for verifying branch trace history buffer information 失效
标题翻译：验证分支跟踪历史缓冲区信息的方法
公开(公告)号：US06247146B1
公开(公告)日：2001-06-12
申请号：US09135065
申请日：1998-08-17
申请人： Travis Wheatley , Michael Wisor , Christopher Gray
发明人： Travis Wheatley , Michael Wisor , Christopher Gray
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： A method and system for verifying the accuracy of trace data generated by execution of a program on a computer under test, one embodiment of the method comprising scanning the trace data to locate bitmap data corresponding to series of consecutive conditional branches and comparing the number of bits representative of these branches to the number of consecutive conditional branches in the instruction sequence. The trace data includes address entries and bitmap entries. The trace data is scanned in reverse chronological order beginning with the most recent entry to locate an address entry preceding one or more bitmaps which represent a most recent series of conditional branches. Beginning with the instruction at the address contained in the address entry, the program instructions are scanned in program order until a conditional branch is encountered. The branch is counted and the trace data is examined to determine whether the branch was taken and scanning is resumed. The scanning and counting of the conditional branches continues until an instruction which generates a non-bitmap entry is encountered. The number of conditional branches is then compared to the number of bits representative of branches to verify that they are equal. In some embodiments, the target addresses of the branch instructions are also checked to verify that they correspond to the target addresses of the corresponding BTHB entries. Preceding bitmap entries are each checked in this manner until all of the trace data has been verified.
摘要翻译：一种用于验证在被测计算机上执行程序产生的跟踪数据的准确性的方法和系统，所述方法的一个实施例包括扫描跟踪数据以定位对应于一系列连续条件分支的位图数据，并比较位数这些分支的代表在指令序列中连续条件分支的数量。跟踪数据包括地址条目和位图条目。跟踪数据以相反的时间顺序扫描，以最新条目开始，以定位表示最近一系列条件分支的一个或多个位图之前的地址条目。从地址条目中包含的地址的指令开始，以程序顺序扫描程序指令，直到遇到条件分支为止。对分支进行计数，并检查跟踪数据以确定分支是否被采集并且扫描被恢复。条件分支的扫描和计数继续，直到遇到生成非位图条目的指令。然后将条件分支的数量与表示分支的比特数进行比较，以验证它们是相等的。在一些实施例中，还检查分支指令的目标地址以验证它们对应于相应BTHB条目的目标地址。前面的位图条目都以这种方式进行检查，直到所有跟踪数据都被验证。

2. 发明授权

US06173395B2 Mechanism to determine actual code execution flow in a computer 有权
标题翻译：确定计算机中实际代码执行流程的机制
公开(公告)号：US06173395B2
公开(公告)日：2001-01-09
申请号：US09135493
申请日：1998-08-17
申请人： Michael Wisor , Travis Wheatley , Dan S. Mudgett
发明人： Michael Wisor , Travis Wheatley , Dan S. Mudgett
IPC分类号： G06F1500
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3648
摘要： A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined. The bitmap entry contains a series of bits, each of which can indicate whether a conditional branch was taken, so that a single bitmap entry can represent a series of conditional branches.
摘要翻译：一种用于使用在执行某些指令时生成的跟踪数据来确定被测计算机中的指令执行顺序的方法和系统。在一个实施例中，该方法包括将轨迹数据中的初始条目定位并以由初始条目指示的指令开始以程序顺序扫描指令。当遇到分支指令时，检查跟踪数据以确定随后执行的指令。如果分支是无条件的，则跟踪数据中的相应地址条目指示下一条指令的地址。如果分支是有条件的，则跟踪数据中的相应位图条目包含一个指示分支是否被采取的位。从该位和指令本身，确定下一条指令。位图条目包含一系列位，每个位可以指示是否采用条件分支，以便单个位图条目可以表示一系列条件分支。

3. 发明授权

US06430705B1 Method for utilizing virtual hardware descriptions to allow for multi-processor debugging in environments using varying processor revision levels 失效
标题翻译：使用虚拟硬件描述以允许在使用不同处理器修订级别的环境中进行多处理器调试的方法
公开(公告)号：US06430705B1
公开(公告)日：2002-08-06
申请号：US09137572
申请日：1998-08-21
申请人： Michael Wisor , Travis Wheatley , James A. Treadway
发明人： Michael Wisor , Travis Wheatley , James A. Treadway
IPC分类号： H02H305
CPC分类号： G06F11/3684
摘要： A method and apparatus for concurrent testing of a plurality of microprocessors, each of which may have a different revision, by creating an abstract base class which specifies the names of a plurality of tests, creating a derived class for each revision and defining each of the tests appropriately for each of the derived classes, instantiating an object from one of the derived classes for each of the microprocessors and executing the tests by reference to the objects. A computer system is configured to be coupled to the microprocessors and, upon execution of a debug/test application on the computer system, the revision of each microprocessor is determined and an object is instantiated from the derived class corresponding to the revision. Each object is thereby dynamically bound to the tests defined for the derived class corresponding to the revision, and references to the tests via the objects automatically execute the test code specific to appropriate revision of the microprocessor.
摘要翻译：一种用于并行测试多个微处理器的方法和装置，每个微处理器可以具有不同的修订，通过创建指定多个测试的名称的抽象基类，为每个修订创建派生类，并定义每个对每个派生类进行适当测试，从每个微处理器的派生类之一实例化一个对象，并通过引用对象来执行测试。计算机系统被配置为耦合到微处理器，并且在计算机系统上执行调试/测试应用程序时，确定每个微处理器的修订，并且从对应于修订的派生类中实例化对象。因此，每个对象动态地绑定到对应于修订版的派生类定义的测试，并且通过对象引用测试自动执行特定于微处理器适当修订的测试代码。

4. 发明授权

US06336212B1 Self modifying code to test all possible addressing modes 失效
标题翻译：自修改代码来测试所有可能的寻址模式
公开(公告)号：US06336212B1
公开(公告)日：2002-01-01
申请号：US09639390
申请日：2000-08-15
申请人： Christopher Gray , Michael Wisor
发明人： Christopher Gray , Michael Wisor
IPC分类号： G06F1136
CPC分类号： G06F11/26
摘要： A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.
摘要翻译：一种用于在微处理器中测试多个寻址模式的方法和系统，包括执行存储在存储器中的测试指令，随后覆盖存储器中的测试指令，然后重新执行测试指令。测试指令存储在代码段内的存储器位置。定义数据段与代码段重叠，并且通过在重叠的数据段内存储数据来覆盖测试指令的一部分。测试指令的覆盖部分标识测试指令的寻址模式，存储的数据表示要测试的下一寻址模式。在x86体系结构中，测试指令的重写部分可以包括一个MODR / M字节和一个SIB字节，每个字节可以取值从00到ff（十六进制）。因此，可以通过顺序增加MODR / M和SIB字节并执行测试指令来测试微处理器的寻址模式。

5. 发明授权

US06128727A Self modifying code to test all possible addressing modes 失效
公开(公告)号：US06128727A
公开(公告)日：2000-10-03
申请号：US137610
申请日：1998-08-21
申请人： Christopher Gray , Michael Wisor
发明人： Christopher Gray , Michael Wisor
IPC分类号： G06F11/00 , G06F11/26 , G06F11/36
CPC分类号： G06F11/26
摘要： A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.

6. 发明授权

US5964859A Allocatable post and prefetch buffers for bus bridges 失效
标题翻译：总线桥可分配的后置缓冲区和预取缓冲区
公开(公告)号：US5964859A
公开(公告)日：1999-10-12
申请号：US960819
申请日：1997-10-30
申请人： Andy Steinbach , Scott Swanstrom , Michael Wisor
发明人： Andy Steinbach , Scott Swanstrom , Michael Wisor
IPC分类号： G06F13/40 , G06F13/14
CPC分类号： G06F13/4059
摘要： A computing system and bus bridge in which the bus bridge includes a buffer pool wherein the storage buffers contained in the buffer pool may be allocated as post buffers or fetch buffers in response to appropriate requests from the bus bridge. In the preferred embodiment, the bus bridge includes a buffer pool control unit adapted to temporarily allocate any of the plurality of storage buffers as either a post buffer or a fetch buffer depending upon the system requirements. Broadly speaking, the present invention contemplates a computing system including a first component connected to a first bus, a second component connected to a second bus, and a bus bridge connected to a first and second busses. The bus bridge includes a buffer pool comprised of a plurality of storage buffers and a buffer pool control unit that is capable of temporarily allocating at least one of the storage buffers as either a post buffer or a fetch buffer in response to system requirement. Preferably, each storage buffer includes corresponding tag information for identifying an origin or destination location within a main memory of the data associated with the storage buffer. In one embodiment, each of the plurality of storage buffers includes corresponding allocation information used by the buffer pool control unit for the temporary allocation of the storage buffers. In a presently preferred embodiment, the allocation information includes an available bit indicative of whether the storage buffers available for allocation and a post/fetch bit indicative of whether an unavailable storage buffer is currently allocated as a post buffer or as a fetch buffer. The allocation information is accessible by the buffer pool control unit and is used by the buffer pool control unit for temporarily allocating the storage buffers.
摘要翻译：一种计算系统和总线桥，其中总线桥包括缓冲池，其中响应于来自总线桥的适当请求，缓冲池中包含的存储缓冲器可以被分配为后缓冲器或提取缓冲器。在优选实施例中，总线桥接器包括缓冲池控制单元，其适于根据系统要求将多个存储缓冲器中的任何一个临时分配为后缓冲器或提取缓冲器。广义而言，本发明考虑了一种包括连接到第一总线的第一组件，连接到第二总线的第二组件和连接到第一和第二总线的总线桥的计算系统。总线桥包括由多个存储缓冲器组成的缓冲池和缓冲池控制单元，该缓冲池控制单元能够响应于系统要求将至少一个存储缓冲器分配为后缓冲器或提取缓冲器。优选地，每个存储缓冲器包括用于标识与存储缓冲器相关联的数据的主存储器内的原始位置或目的地位置的相应标签信息。在一个实施例中，多个存储缓冲器中的每一个包括由缓冲池控制单元用于临时分配存储缓冲器的相应分配信息。在当前优选实施例中，分配信息包括指示可用于分配的存储缓冲器的可用位以及指示当前是否将不可用存储缓冲器分配为后缓冲器或作为读取缓冲器的后/取位。分配信息可由缓冲池控制单元访问，并由缓冲池控制单元用于临时分配存储缓冲区。

7. 发明授权

US5920891A Architecture and method for controlling a cache memory 失效
标题翻译：用于控制高速缓冲存储器的体系结构和方法
公开(公告)号：US5920891A
公开(公告)日：1999-07-06
申请号：US650523
申请日：1996-05-20
申请人： Andy Steinbach , Scott Swanstrom , Michael Wisor
发明人： Andy Steinbach , Scott Swanstrom , Michael Wisor
IPC分类号： G06F12/08 , G06F13/14 , G06F13/38
CPC分类号： G06F12/0835
摘要： A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.
摘要翻译：一种高速缓冲存储器系统，包括用于连接到总线主机的第一总线和用于连接到系统存储器的第二总线。系统存储器包括多个可高速缓存的存储器位置。总线桥提供第一总线和第二总线之间的接口。用于缓存存储在可高速缓存存储单元中的数据的高速缓冲存储器控制器被连接到系统存储器。高速缓存存储器控制器包括直接耦合到第一总线的监听控制电路，用于在第一总线上窥探总线事务，并且进一步耦合到第二总线，用于在所述第二总线上窥探总线事务。

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