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1. 发明授权

US5905898A Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效
标题翻译：基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
IPC分类号： G06F13/26 , G06F15/17 , G06F3/00
CPC分类号： G06F13/26 , G06F15/17
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译：提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。用于引用中断请求的中断请求标识代码按其优先顺序存储。每个嵌套缓冲区只需要等于优先级数量的条目数。

2. 发明授权

US5557757A High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus 失效
标题翻译：高性能集成处理器架构，包括用于产生信号以控制次级非多路复用外部总线的子总线控制单元
公开(公告)号：US5557757A
公开(公告)日：1996-09-17
申请号：US190647
申请日：1994-02-02
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , G06F13/4027
摘要： An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
摘要翻译：集成处理器，采用总线接口单元，通过外部外部互连总线与复用的地址/数据线进行高性能数据传输。可以是PCI标准总线的外围互连总线适应在集成处理器的内部总线与PCI外围设备之间的数据传输。集成处理器还包括一个子总线控制单元，该子总线控制单元产生一组边带控制信号，这些边带控制信号允许诸如ISA总线的较低性能辅助总线的外部导出，而不需要用于次级的完整的一组外部引脚总线上的集成处理器。辅助总线的推导是通过由边带控制信号控制的外部数据缓冲器和外部地址锁存来实现的。不需要用于辅助总线的集成处理器的独立地址和数据线。因此，高性能外围设备由集成处理器以及性能更低，成本更低的外设支持，而不会显着增加集成处理器的引脚数。因此，在支持广泛的外围设备的情况下，集成处理器的整体成本保持较低。

3. 发明授权

US5561821A System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus 失效
标题翻译：通过分别在本地总线上驱动DMA配置寄存器的地址和存储地址来执行I / O访问和存储器访问的系统
公开(公告)号：US5561821A
公开(公告)日：1996-10-01
申请号：US145375
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.
摘要翻译：提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。

4. 发明授权

US5561819A Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller 失效
标题翻译：计算机系统在通过在DMA控制器中驱动本地总线上的范围内的地址来禁用非参与的外设的I / O寻址技术期间选择外围设备的字节通道
公开(公告)号：US5561819A
公开(公告)日：1996-10-01
申请号：US145376
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36 , G06F13/40
CPC分类号： G06F13/28 , G06F13/4018
摘要： A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.
摘要翻译：直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。外围设备响应地在指定的字节通道处接收或提供数据。结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。

5. 发明授权

US5894577A Interrupt controller with external in-service indication for power management within a computer system 失效
标题翻译：具有外部在线指示的中断控制器，用于计算机系统内的电源管理
公开(公告)号：US5894577A
公开(公告)日：1999-04-13
申请号：US125336
申请日：1993-09-22
申请人： James R MacDonald , Douglas D. Gephardt , Dan S. Mudgett
发明人： James R MacDonald , Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F1/04 , G06F1/32 , G06F9/48 , G06F13/24 , G06F13/26 , G06F9/46
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译：中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。提供在线寄存器用于存储由微处理器服务的任何请求线的标识。在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

6. 发明授权

US5765003A Interrupt controller optimized for power management in a computer system or subsystem 失效
标题翻译：针对计算机系统或子系统中的电源管理优化的中断控制器
公开(公告)号：US5765003A
公开(公告)日：1998-06-09
申请号：US671831
申请日：1996-10-09
申请人： James R. MacDonald , Douglas D. Gephardt , Dan S. Mudgett
发明人： James R. MacDonald , Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F1/04 , G06F1/32 , G06F9/48 , G06F13/24 , G06F13/26
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/325 , G06F1/3287 , G06F13/24 , G06F13/26 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed. Using this information, the power management unit advantageously stops unused clock signals and/or removes power from inactive circuit portions when an interrupt routine completes without having to estimate the time of completion. By accurately stopping unused clock signals and removing power, a reduction in the overall power consumption of the computer system can be attained.
摘要翻译：中断控制器包括一个中断请求寄存器，用于通过一组请求线接收各种外设或I / O设备的中断请求。还提供了一个优先级解算器，用于比较中断线的优先级，在待机模式下锁定较低优先级的请求，并指导服务于最高优先级。提供在线寄存器用于存储由微处理器服务的任何请求线的标识。在一个实施例中，一组信号线耦合在制造中断控制器的集成电路的在役寄存器和外部端子之间。功率管理单元可以耦合到集成电路的外部引脚，从而接收关于当前被服务的中断请求的实时信息，并且关于完成的中断服务程序。使用该信息，当中断程序完成时，功率管理单元有利地停止未使用的时钟信号和/或从非活动电路部分去除功率，而不必估计完成时间。通过准确地停止未使用的时钟信号和去除功率，可以实现计算机系统的整体功耗的降低。

7. 发明授权

US5655142A High performance derived local bus and computer system employing the same 失效
标题翻译：高性能派生本地总线和采用相同的计算机系统
公开(公告)号：US5655142A
公开(公告)日：1997-08-05
申请号：US705884
申请日：1996-08-28
申请人： Douglas D. Gephardt , Dan S. Mudgett
发明人： Douglas D. Gephardt , Dan S. Mudgett
IPC分类号： G06F13/38 , G06F13/42 , G06F15/78 , G06F13/24
CPC分类号： G06F13/4217 , G06F13/423 , G06F15/7832
摘要： An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus. A latch is coupled to the multiplexed address/data (A/D) lines of the PCI bus and includes a set of output lines coupled to the address input lines of the externally connected peripheral device. The external latch is latched by the loading signal. The cycle definition signals of the PCI bus are further latched within the external latch to provide memory/IO and read/write signals to the external peripheral device. The data lines of the peripheral device may be connected directly to the multiplexed address/data lines of the PCI bus.
摘要翻译：提供了一种集成处理器，其包括CPU核心，耦合到CPU核心的本地总线以及耦合到本地总线的诸如存储器控制器，直接存储器访问控制器和中断控制器的各种外设。还提供总线接口单元以在CPU本地总线和PCI标准复用的外围总线之间进行接口。 CPU核心，存储器控制器，直接存储器访问控制器，中断控制器和总线接口单元都被并入公共集成电路芯片。还提供了本地总线控制单元，其能够与在PCI总线上执行的某些总线周期同步地产生加载信号和地址选通信号。本地总线控制单元允许通过PCI总线连接与CPU本地总线协议兼容的外部外设。锁存器耦合到PCI总线的复用的地址/数据（A / D）线，并且包括耦合到外部连接的外围设备的地址输入线的一组输出线。外部锁存器被加载信号锁存。 PCI总线的周期定义信号进一步锁存在外部锁存器内，以向外部外围设备提供存储/ IO和读/写信号。外围设备的数据线可以直接连接到PCI总线的复用地址/数据线。

8. 发明授权

US5778236A Multiprocessing interrupt controller on I/O bus 失效
标题翻译： I / O总线上的多处理中断控制器
公开(公告)号：US5778236A
公开(公告)日：1998-07-07
申请号：US649787
申请日：1996-05-17
申请人： Douglas D. Gephardt , Rodney W. Schmidt
发明人： Douglas D. Gephardt , Rodney W. Schmidt
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24
摘要： A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for multiple CPUs. The CPUs are coupled to a host bus which in turn is coupled to the expansion bus by means of a bus bridge. An arbiter is coupled to the host bus for arbitrating bus mastership amongst the CPUs. CPU host owner identification for access to the storage locations is transferred across bus bridge to the programmable interrupt controller synchronized with the buffered address and data.
摘要翻译：一种多处理计算机系统，其包括耦合到扩展总线的中断控制器。可编程中断控制器在多个CPU的同一地址具有多个存储位置。 CPU耦合到主机总线，主机总线又通过总线桥耦合到扩展总线。仲裁器耦合到主机总线，用于仲裁CPU之间的总线主控权。用于访问存储位置的CPU主机所有者标识通过总线桥传输到与缓冲的地址和数据同步的可编程中断控制器。

9. 发明授权

US5721931A Multiprocessing system employing an adaptive interrupt mapping mechanism and method 失效
标题翻译：多处理系统采用自适应中断映射机制和方法
公开(公告)号：US5721931A
公开(公告)日：1998-02-24
申请号：US408003
申请日：1995-03-21
申请人： Douglas D. Gephardt , Rodney W. Schmidt
发明人： Douglas D. Gephardt , Rodney W. Schmidt
IPC分类号： G06F15/16 , G06F9/46 , G06F13/24 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： A symmetrical multiprocessing system is provided that includes a central interrupt control unit. The central interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt sources include a plurality of peripheral devices coupled to a first peripheral bus, such as a PCI bus. The interrupt sources also include devices coupled to a second peripheral bus, such as an ISA bus. The central interrupt control unit is operative in two modes. In a first mode, referred to as a pass through mode, interrupts from ISA peripheral devices are provided through an interrupt controller, such as cascaded type 8259 interrupt controllers, to the central interrupt control unit. The central interrupt control unit then passes the interrupt directly to a master processing unit. PCI interrupts are provided through a PCI mapper to other available interrupt inputs of the interrupt controller. The pass through mode advantageously allows backwards compatibility of the system with traditional operating systems such as DOS. During the advanced operating mode, the central interrupt control unit causes the PCI mapper to be disabled. In the advanced mode, interrupts from both PCI devices and ISA devices are provided directly to the central interrupt control unit. Since the PCI mapper is disabled during the advanced mode, additional ISA peripheral devices may be supported within the system without contending with PCI interrupts.
摘要翻译：提供了包括中央中断控制单元的对称多处理系统。中央中断控制单元耦合到多个处理单元和多个中断源。中断源包括耦合到诸如PCI总线的第一外围总线的多个外围设备。中断源还包括耦合到第二外围总线的设备，例如ISA总线。中央中断控制单元有两种模式。在被称为通过模式的第一模式中，来自ISA外围设备的中断通过诸如级联型8259中断控制器的中断控制器提供给中央中断控制单元。中央中断控制单元然后将中断直接传递到主处理单元。 PCI中断通过PCI映射器提供给中断控制器的其他可用中断输入。通过模式有利地允许系统与诸如DOS的传统操作系统的向后兼容性。在高级操作模式下，中央中断控制单元使PCI映射器被禁用。在高级模式下，两个PCI设备和ISA设备的中断都直接提供给中央中央控制单元。由于在高级模式下禁用了PCI映射器，所以系统中可能会支持额外的ISA外围设备，而不会与PCI中断相冲突。

10. 发明授权

US5768584A ROM chip enable encoding method and computer system employing the same 失效
标题翻译： ROM芯片使能编码方法和采用该方法的计算机系统
公开(公告)号：US5768584A
公开(公告)日：1998-06-16
申请号：US710047
申请日：1996-09-10
申请人： James R. MacDonald , Douglas D. Gephardt
发明人： James R. MacDonald , Douglas D. Gephardt
IPC分类号： G11C17/00 , G06F9/445 , G06F12/00 , G06F12/06
CPC分类号： G06F9/4401 , G06F12/0653
摘要： A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines. In this configuration, each output line of the decoder is coupled to a respective bank enable input line of the ROM banks. In either configuration, the chip enable lines are driven in a mutually exclusive relationship during system boot to access the boot code (stored within one of the ROM banks). Subsequently, the encoding of the chip enable signals at the chip enable output lines of the memory controller is dependent upon configuration information stored in a configuration register.
摘要翻译：非易失性存储器芯片使能编码方法允许在公共存储器阵列中存储引导代码和用户应用软件。芯片使能编码方法还允许在非易失性存储器阵列内提供可变数量的存储体，并且在固件选择阵列配置之前允许系统上电并执行引导代码。在一个实施例中，存储器控制器包括用于选择性地启用多个ROM组的四个芯片使能输出线。其中一个ROM库包括在系统引导期间由系统微处理器执行的引导代码。如果用户需要由四个ROM组组成的ROM阵列，则每个ROM组连接有单独的芯片使能输出线。如果用户需要由例如八个ROM组组成的ROM阵列，则外部解码器可以连接到四个芯片使能输出线。在该配置中，解码器的每个输出线耦合到ROM组的相应的bank使能输入线。在任一配置中，芯片使能线在系统引导期间以相互排斥的关系被驱动以访问引导代码（存储在ROM库之一内）。随后，存储器控制器的芯片使能输出线处的芯片使能信号的编码取决于存储在配置寄存器中的配置信息。

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