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11. 发明授权

US07339232B2 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07339232B2
公开(公告)日：2008-03-04
申请号：US11256554
申请日：2005-10-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.
摘要翻译：提供具有多位非易失性存储单元的半导体器件。半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。多个晶体管各自包括至少一个控制栅极和至少一个电荷存储区域。电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

12. 发明申请

US20060108610A1 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
公开(公告)号：US20060108610A1
公开(公告)日：2006-05-25
申请号：US11329217
申请日：2006-01-10
申请人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
发明人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/28273 , H01L21/0214 , H01L21/3144 , H01L29/513 , H01L29/7881
摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

13. 发明授权

US07041557B2 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
标题翻译：使用热处理制造薄介电层的方法和使用该方法形成的半导体器件
公开(公告)号：US07041557B2
公开(公告)日：2006-05-09
申请号：US10832952
申请日：2004-04-27
申请人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
发明人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
IPC分类号： H01L21/366
CPC分类号： H01L21/0214 , H01L21/02249 , H01L21/02252 , H01L21/28273 , H01L21/3144
摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.
摘要翻译：在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

14. 发明申请

US20170345475A1 RESISTIVE-TYPE MEMORY DEVICES AND INTEGRATED CIRCUITS INCLUDING THE SAME 审中-公开
公开(公告)号：US20170345475A1
公开(公告)日：2017-11-30
申请号：US15402231
申请日：2017-01-09
申请人： Choong-Jae LEE , Gwan-Hyeob KOH , Bo-Young SEO , Yong-Kyu LEE
发明人： Choong-Jae LEE , Gwan-Hyeob KOH , Bo-Young SEO , Yong-Kyu LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/005 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/22 , G11C13/0002
摘要： A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.

15. 发明授权

US09583534B2 Semiconductor device including magneto-resistive device 有权
标题翻译：半导体装置包括磁阻装置
公开(公告)号：US09583534B2
公开(公告)日：2017-02-28
申请号：US14795882
申请日：2015-07-09
申请人： Choong-jae Lee , Hong-kook Min , Bo-young Seo , Aliaksei Ivaniukovich , Yong-kyu Lee
发明人： Choong-jae Lee , Hong-kook Min , Bo-young Seo , Aliaksei Ivaniukovich , Yong-kyu Lee
IPC分类号： H01L27/22 , H01L43/02 , H01L43/08 , H01L29/10 , H01L29/78
CPC分类号： H01L27/228 , H01L29/1045 , H01L29/7833 , H01L29/7835 , H01L43/08
摘要： A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.
摘要翻译：半导体器件包括能够以低功率执行多个功能的磁阻器件。半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体电阻器件连接到单元晶体管的第二杂质区域。相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

16. 发明申请

US20160126289A1 SEMICONDUCTOR DEVICE INCLUDING MAGNETO-RESISTIVE DEVICE 有权
标题翻译：包括磁电阻器件的半导体器件
公开(公告)号：US20160126289A1
公开(公告)日：2016-05-05
申请号：US14795882
申请日：2015-07-09
申请人： Choong-jae LEE , Hong-kook MIN , Bo-young SEO , Aliaksei IVANIUKOVICH , Yong-kyu LEE
发明人： Choong-jae LEE , Hong-kook MIN , Bo-young SEO , Aliaksei IVANIUKOVICH , Yong-kyu LEE
IPC分类号： H01L27/22 , H01L29/08 , H01L29/78 , H01L43/02
CPC分类号： H01L27/228 , H01L29/1045 , H01L29/7833 , H01L29/7835 , H01L43/08
摘要： A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.
摘要翻译：半导体器件包括能够以低功率执行多个功能的磁阻器件。半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体电阻器件连接到单元晶体管的第二杂质区域。相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

17. 发明申请

US20120018797A1 NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造和驱动方法
公开(公告)号：US20120018797A1
公开(公告)日：2012-01-26
申请号：US13168257
申请日：2011-06-24
申请人： Tea-Kwang YU , Yong-Tae KIM , Byung-Sup SHIM , Yong-Kyu LEE , Bo-Young SEO , Ji-Hoon PARK
发明人： Tea-Kwang YU , Yong-Tae KIM , Byung-Sup SHIM , Yong-Kyu LEE , Bo-Young SEO , Ji-Hoon PARK
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28518 , H01L21/743 , H01L21/76224 , H01L21/76895 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.
摘要翻译：非易失性存储器件包括限定半导体衬底中的有源区的器件隔离膜，形成在有源区的上部并具有第一导电类型的凹穴阱区，形成在有源区上并延伸到相交的栅电极有源区，隧道绝缘膜，电荷存储膜和顺序地设置在有源区和栅电极之间的阻挡绝缘膜，分别形成在有源区和栅极的第一区和第二区中的源区和漏区在所述栅电极的两侧露出，并且具有与所述第一导电类型相反的第二导电类型的凹穴结区，形成在与所述源极区相邻的所述第一区域中并且与所述凹穴阱区接触并且具有第一导电型，以及形成在第一区域中的金属硅化物层，并且与源极区域和凹穴阱结区域接触。

18. 发明授权

US07553725B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07553725B2
公开(公告)日：2009-06-30
申请号：US11488911
申请日：2006-07-18
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.
摘要翻译：非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。单元栅极图案和选择线之间的距离小于选择线的宽度。

19. 发明授权

US07320913B2 Methods of forming split-gate non-volatile memory devices 失效
标题翻译：形成分闸非易失性存储器件的方法
公开(公告)号：US07320913B2
公开(公告)日：2008-01-22
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

20. 发明申请

US20070195595A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070195595A1
公开(公告)日：2007-08-23
申请号：US11600427
申请日：2006-11-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.
摘要翻译：非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

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