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11. 发明授权

US6028453A Charge recycling differential logic (CRDL) circuit having true single-phase clocking scheme 失效
标题翻译：充电回收差分逻辑（CRDL）电路具有真正的单相时钟方案
公开(公告)号：US6028453A
公开(公告)日：2000-02-22
申请号：US950973
申请日：1997-10-15
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： H03K19/20 , G06F1/28 , G06F7/50 , G06F7/507 , G11C11/412 , H03K19/00 , H03K19/096 , H03K19/173 , H03K19/21 , H03K19/094
CPC分类号： G06F7/507 , G06F7/501 , G06F7/503 , G06F7/505 , G11C11/412 , H03K19/0019 , H03K19/0963 , H03K19/1738 , H03K19/215 , G06F2207/3872 , G06F2207/3884
摘要： A novel logic family, called Charge Recycling Differential Logic (CRDL) circuit, reduces power consumption by utilizing a charge recycling technique and has a speed comparable to those of conventional dynamic logic circuits. The CRDL circuit also has improved noise margin due to inherently static operation. An 8-bit Manchester carry chain and full adders were fabricated using a 0.8 .mu.m single-poly double-metal n-well CMOS technology. The measurement results indicate about 16-48% improvements in power-delay product are obtained compared with Differential Cascode Voltage Switch (DCVS) circuit. Further, a circuit operating under a true single-phase clock signal includes a plurality of pipelined stages having a plurality of function blocks to implement a prescribed function. The function blocks are implemented using the novel CRDL circuit. An adder based on the CRDL circuit provided improved performance and reduced power consumption compared to an adder based on the DCVS circuit.
摘要翻译：称为电荷回收差分逻辑（CRDL）电路的新型逻辑系列通过利用电荷回收技术降低功耗，并且具有与常规动态逻辑电路相当的速度。由于固有的静态操作，CRDL电路还具有改善的噪声容限。使用0.8μm单多晶双金属n阱CMOS技术制造了8位曼彻斯特携带链和全加法器。测量结果表明，与差分串联电压开关（DCVS）电路相比，获得了功率延迟产品的16-48％的改进。此外，在真正的单相时钟信号下工作的电路包括具有多个功能块的多个流水线级，以实现规定的功能。功能块使用新颖的CRDL电路实现。与基于DCVS电路的加法器相比，基于CRDL电路的加法器提供了改进的性能和降低的功耗。

12. 发明授权

US08441279B2 Scan flip-flop circuits and scan test circuits including the same 有权
标题翻译：扫描触发器电路和扫描测试电路，包括它们
公开(公告)号：US08441279B2
公开(公告)日：2013-05-14
申请号：US13154731
申请日：2011-06-07
申请人： Hoi-Jin Lee , Bai-Sun Kong
发明人： Hoi-Jin Lee , Bai-Sun Kong
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K3/356182
摘要： A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.
摘要翻译：扫描触发器电路包括输入单元和输出单元。输入单元根据操作模式选择数据输入信号和扫描输入信号之一，并基于所选择的信号产生中间信号。输出单元基于中间信号产生输出信号，并根据操作模式选择数据输出端和扫描输出端之一，以通过所选择的输出端提供输出信号。所选择的输出端子处的电压电平在第一电压电平和第二电压电平之间双向转换。未选择的输出端子处的电压电平在第一电压电平和第二电压电平之间单向转变。

13. 发明申请

US20120268182A1 CLOCK GATED CIRCUIT AND DIGITAL SYSTEM HAVING THE SAME 有权
标题翻译：时钟门控电路和数字系统
公开(公告)号：US20120268182A1
公开(公告)日：2012-10-25
申请号：US13440007
申请日：2012-04-05
申请人： HOIJIN LEE , Bai-Sun Kong
发明人： HOIJIN LEE , Bai-Sun Kong
IPC分类号： H03K3/00 , H03H11/26
CPC分类号： H03K3/356121
摘要： A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.
摘要翻译：时钟选通电路包括脉冲发生器和脉冲电平移位器。脉冲发生器由第一电源电压驱动，并被配置为接收时钟信号以产生脉冲和反相脉冲。脉冲电平移位器由比第一电源电压高的第二电源电压驱动，并被配置为接收脉冲和反相脉冲，并响应于使能信号转换脉冲电平。

14. 发明授权

US08130028B2 CMOS charge pump with improved latch-up immunity 有权
标题翻译： CMOS电荷泵具有提高的闭锁抑制能力
公开(公告)号：US08130028B2
公开(公告)日：2012-03-06
申请号：US12691937
申请日：2010-01-22
申请人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
发明人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.
摘要翻译：提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

15. 发明授权

US07928795B2 Semiconductor device for charge pumping 有权
标题翻译：用于电荷泵浦的半导体器件
公开(公告)号：US07928795B2
公开(公告)日：2011-04-19
申请号：US12458533
申请日：2009-07-15
申请人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
发明人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.
摘要翻译：提供一种用于进行电荷泵送的半导体器件。半导体器件可以包括第一泵送单元，第二泵送单元和控制器。第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。控制器可以被配置为控制第一和第二泵送单元。第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。此外，传输单元可以被配置为控制升压电压的输出。

16. 发明授权

US07446607B2 Regulated cascode circuit, an amplifier including the same, and method of regulating a cascode circuit 有权
公开(公告)号：US07446607B2
公开(公告)日：2008-11-04
申请号：US11799993
申请日：2007-05-03
申请人： Mu-Kyeng Jung , Jae-Whui Kim , Bai-Sun Kong
发明人： Mu-Kyeng Jung , Jae-Whui Kim , Bai-Sun Kong
IPC分类号： H03F3/45
CPC分类号： H03F1/223 , H03F3/45192 , H03F3/45632 , H03F2200/513 , H03F2203/45052 , H03F2203/45292 , H03F2203/45302 , H03F2203/45652
摘要： A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.

17. 发明授权

US06717448B2 Data output method and data output circuit for applying reduced precharge level 有权
标题翻译：数据输出方式和数据输出电路，用于降低预充电水平
公开(公告)号：US06717448B2
公开(公告)日：2004-04-06
申请号：US10212166
申请日：2002-08-06
申请人： Nak-won Heo , Bai-sun Kong
发明人： Nak-won Heo , Bai-sun Kong
IPC分类号： H03K3289
CPC分类号： H03K3/356139 , H03K3/356191 , H03K3/3562
摘要： A data output method and data output circuit capable of increasing data output speed by reducing clock power while increasing sensing speed are provided. The data output method includes (a) precharging output terminals to a precharge voltage lower than a supply voltage; and (b) outputting differential output signals to the output terminals in response to differential input signals. In step (a) the output terminals are precharged in response to a clock signal having a first state, and in step (b) the differential signals are output to the output terminals in response to the clock signal having a second state. The voltage swing of the clock signal is set lower than the precharge voltage. The method further includes latching the differential output signals.
摘要翻译：提供了一种数据输出方法和数据输出电路，能够通过在增加感测速度的同时降低时钟功率来提高数据输出速度。数据输出方法包括（a）将输出端子预充电到低于电源电压的预充电电压; 和（b）响应差分输入信号将差分输出信号输出到输出端。在步骤（a）中，响应于具有第一状态的时钟信号对输出端子进行预充电，并且在步骤（b）中，响应于具有第二状态的时钟信号将差分信号输出到输出端子。时钟信号的电压摆幅设定为低于预充电电压。该方法还包括锁存差分输出信号。

18. 发明授权

US6016065A Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same 有权
标题翻译：收费回收差分逻辑（CRDL）电路和使用其的存储元件和器件
公开(公告)号：US6016065A
公开(公告)日：2000-01-18
申请号：US234517
申请日：1999-01-21
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： G11C11/41 , G11C7/00 , G11C11/412 , H03K3/356 , H03K19/00 , H03K19/0944 , H03K19/096 , H03K19/173 , H03K19/21
CPC分类号： G11C11/412 , H03K19/0019 , H03K19/0963 , H03K19/1738 , H03K19/215 , H03K3/356147 , G06F2207/3884
摘要： A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.
摘要翻译：根据优选实施例的用于半导体器件的存储元件表现出较小的噪声并且以更快的速度消耗更少的功率。当输入电极的输入信号从（i）第一信号电平之一转换到第二信号电平时，第一电路将先前状态的第一存储节点维持在相同的信号电平，以及（ii）第三信号电平转换到第二信号电平。第一电路包括耦合到输入电极的第一多个晶体管，以及耦合到所述第一多个晶体管并在第一存储节点处彼此耦合的第一对晶体管。当所述输入信号从所述第二信号电平转换到所述第一信号电平时，耦合到所述第一电路的第二电路将所述第一存储节点的状态改变为（i）第一信号电平之一，以及（ii）第三信号电平，输入信号从第二信号电平转换到第三信号电平。

19. 发明申请

US20100271069A1 INPUT/OUTPUT CIRCUIT AND INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
标题翻译：输入/输出电路和集成电路设备，包括它们
公开(公告)号：US20100271069A1
公开(公告)日：2010-10-28
申请号：US12714878
申请日：2010-03-01
申请人： Joung Yeal Kim , Young Hyun Jun , Bai Sun Kong
发明人： Joung Yeal Kim , Young Hyun Jun , Bai Sun Kong
IPC分类号： H03K19/0175 , G11C7/00
CPC分类号： H04L25/0278 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/22 , H03K19/017509
摘要： An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.
摘要翻译：输入/输出电路包括连接到具有上拉和下拉晶体管的上拉和下拉电路的I / O节点。通过I / O节点发送和接收数据。电平移位器提供包括电源电压和高于电源电压的高电压的电压。信号控制电路控制施加到上拉和下拉电路的电压电平。在数据输入模式期间，在I / O节点处接收数据，并且上拉晶体管被偏置在高电压以截止上拉晶体管。在数据输出模式下，在I / O节点输出数据，当输出数据为低电平时，下拉晶体管将I / O节点拉低至地，当输出数据为高电平时，上拉晶体管被激活。

20. 发明申请

US20090185437A1 CLOCK-BASED DATA STORAGE DEVICE, DUAL PULSE GENERATION DEVICE, AND DATA STORAGE DEVICE 有权
标题翻译：基于时钟的数据存储设备，双脉冲发生器件和数据存储器件
公开(公告)号：US20090185437A1
公开(公告)日：2009-07-23
申请号：US12034556
申请日：2008-02-20
申请人： Bai Sun Kong , Sung Chan Kang , Byung Hwa Jung
发明人： Bai Sun Kong , Sung Chan Kang , Byung Hwa Jung
IPC分类号： G11C7/00 , G11C8/00 , H03K3/00
CPC分类号： G11C11/412 , H03K3/012 , H03K3/356121
摘要： Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted f roars the pull-down unit as well as the pull-down unit.
摘要翻译：公开了一种基于时钟的数据存储装置，其包括双脉冲发生装置和具有两个动态节点用于事先充电/放电的数据扩充装置。基于时钟的数据存储装置包括双脉冲发生单元，其延迟时钟信号，然后通过使用延迟的时钟信号输出对应于时钟信号的反相的第一时钟信号和对应于时钟信号的第二时钟信号基于从双脉冲发生单元输出的第一时钟信号和输入了贝贝的输入数据信号，上拉等待输出端口的上拉输出信号的上拉等待时间信号移位，下拉单元用于基于从双脉冲发生单元输出的第二时钟信号和输入的输入数据信号向输出端口输出下拉输出信号;以及锁存单元，其设置在上拉和下拉下拉单元和输出端口，以便存储输出的至少一个输出信号和下拉单元以及下拉单元。

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