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1. 发明授权

US07928795B2 Semiconductor device for charge pumping 有权
标题翻译：用于电荷泵浦的半导体器件
公开(公告)号：US07928795B2
公开(公告)日：2011-04-19
申请号：US12458533
申请日：2009-07-15
申请人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
发明人： Joung-yeal Kim , Young-hyun Jun , Bai-sun Kong
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.
摘要翻译：提供一种用于进行电荷泵送的半导体器件。半导体器件可以包括第一泵送单元，第二泵送单元和控制器。第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。控制器可以被配置为控制第一和第二泵送单元。第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。此外，传输单元可以被配置为控制升压电压的输出。

2. 发明授权

US07030643B2 Output buffer circuits including logic gates having balanced output nodes 有权
标题翻译：输出缓冲电路包括具有平衡输出节点的逻辑门
公开(公告)号：US07030643B2
公开(公告)日：2006-04-18
申请号：US10701321
申请日：2003-11-04
申请人： Joung-yeal Kim
发明人： Joung-yeal Kim
IPC分类号： H03K19/003
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A buffer circuit may include an output terminal, a pull-up transistor, a pull-down transistor, and first and second logic gates. The pull-up transistor is connected between the output terminal and a supply voltage, and the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal. The pull-down transistor is connected between the output terminal and a reference voltage, and the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal. The first logic gate may generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and the first logic gate may include a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node. The second logic gate may generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal, and the second logic gate may include a plurality of serially connected transistors in a path between the supply voltage and the second output node.
摘要翻译：缓冲电路可以包括输出端子，上拉晶体管，下拉晶体管以及第一和第二逻辑门。上拉晶体管连接在输出端子和电源电压之间，并且上拉晶体管响应于上拉控制信号将输出端子拉至电源电压。下拉晶体管连接在输出端子和参考电压之间，并且下拉晶体管响应于下拉控制信号将输出端子下拉到参考电压。第一逻辑门可以响应于控制信号和数据信号而在第一输出节点产生上拉控制信号，并且第一逻辑门可以包括电源电压和电源电压之间的电气路径中的多个串联连接的晶体管第一个输出节点。第二逻辑门可以响应于数据信号和控制信号的反相而在第二输出节点处产生下拉控制信号，并且第二逻辑门可以包括在电源电压之间的路径中的多个串联连接的晶体管和第二输出节点。

3. 发明授权

US08891324B2 Memory device from which dummy edge memory block is removed 有权
标题翻译：去除虚拟边缘存储器块的存储器件
公开(公告)号：US08891324B2
公开(公告)日：2014-11-18
申请号：US13915338
申请日：2013-06-11
申请人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
发明人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
IPC分类号： G11C7/00 , G11C5/06 , G11C7/06 , H01L27/02 , H01L27/105 , G11C7/18 , G11C11/4091 , H01L27/108
CPC分类号： G11C5/063 , G11C7/062 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897 , Y10T29/41
摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.
摘要翻译：一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管，电容器块电连接到边缘检测放大块。

4. 发明申请

US20070043921A1 Wave pipelined output circuit of synchronous memory device 有权
标题翻译：同步存储设备的波形流水线输出电路
公开(公告)号：US20070043921A1
公开(公告)日：2007-02-22
申请号：US11504897
申请日：2006-08-16
申请人： Joung-yeal Kim , Seong-jin Jang
发明人： Joung-yeal Kim , Seong-jin Jang
IPC分类号： G06F13/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1072
摘要： Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.
摘要翻译：提供了同步存储器件的波形流水线输出电路。在波长流水线输出电路中，同步存储装置的高频模式传送数据的路径与同步存储装置的低频模式下的数据传送路径分离。包括在高频模式的数据输出路径中的寄存器数量减少，并且用于寄存器的数据输入/输出的控制信号的数量也减少。因此，降低高频模式下的数据输出路径的负载，以改善高频操作并减小输出电路的芯片面积。

5. 发明授权

US07423927B2 Wave pipelined output circuit of synchronous memory device 有权
标题翻译：同步存储设备的波形流水线输出电路
公开(公告)号：US07423927B2
公开(公告)日：2008-09-09
申请号：US11504897
申请日：2006-08-16
申请人： Joung-yeal Kim , Seong-jin Jang
发明人： Joung-yeal Kim , Seong-jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1072
摘要： Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.
摘要翻译：提供了同步存储器件的波形流水线输出电路。在波长流水线输出电路中，同步存储装置的高频模式传送数据的路径与同步存储装置的低频模式下的数据传送路径分离。包括在高频模式的数据输出路径中的寄存器数量减少，并且用于寄存器的数据输入/输出的控制信号的数量也减少了。因此，降低高频模式下的数据输出路径的负载，以改善高频操作并减小输出电路的芯片面积。

6. 发明授权

US08482951B2 Memory device from which dummy edge memory block is removed 有权
标题翻译：去除虚拟边缘存储器块的存储器件
公开(公告)号：US08482951B2
公开(公告)日：2013-07-09
申请号：US13023738
申请日：2011-02-09
申请人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
发明人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C7/062 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897 , Y10T29/41
摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.
摘要翻译：一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管，电容器块电连接到边缘检测放大块。

7. 发明授权

US07552368B2 Systems and methods for simultaneously testing semiconductor memory devices 失效
标题翻译：同时测试半导体存储器件的系统和方法
公开(公告)号：US07552368B2
公开(公告)日：2009-06-23
申请号：US10823076
申请日：2004-04-13
申请人： Joung-yeal Kim , Kyoung-ho Kim
发明人： Joung-yeal Kim , Kyoung-ho Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/2602
摘要： A method for testing a memory cell array of a semiconductor memory device in a parallel bit test mode includes selecting first data from one of a plurality of memory regions in the memory array for output from the memory device via an input/output pad, and then selecting second data from another of the plurality of memory regions for output via the input/output pad. The first and second data can be selected from memory regions sharing a row select or a column select control line. Alternatively, one of the first and second data can be selected from memory regions sharing a row select control line, and the other can be selected from memory regions sharing a column select control line. Therefore, a parallel bit test can be performed using fewer input/output pads, and a larger number of semiconductor memory devices can simultaneously be tested. Related circuits are also discussed.
摘要翻译：用于以并行位测试模式测试半导体存储器件的存储单元阵列的方法包括从存储器阵列中的多个存储器区域之一中选择第一数据，以经由输入/输出焊盘从存储器件输出，然后从所述多个存储器区域中的另一个存储区域中选择第二数据，以经由所述输入/输出焊盘输出。可以从共享行选择或列选择控制线的存储器区域中选择第一和第二数据。或者，可以从共享行选择控制线的存储器区域中选择第一和第二数据中的一个，并且另一个可以从共享列选择控制线的存储器区域中选择。因此，可以使用更少的输入/输出焊盘来执行并行位测试，并且可以同时测试更多数量的半导体存储器件。还讨论了相关电路。

8. 发明授权

US06483353B2 Current sense amplifier circuits containing latches for improving stability and amplification in semiconductor devices 失效
标题翻译：包含用于提高半导体器件稳定性和放大的锁存器的电流读出放大器电路
公开(公告)号：US06483353B2
公开(公告)日：2002-11-19
申请号：US09999650
申请日：2001-10-30
申请人： Joung-yeal Kim , Chul-soo Kim
发明人： Joung-yeal Kim , Chul-soo Kim
IPC分类号： G01R1900
CPC分类号： H03K3/356113 , G11C7/065 , G11C2207/063
摘要： The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.
摘要翻译：本发明提供一种电流检测放大器，其包括具有交叉耦合栅极和漏极的第一和第二检测晶体管。电流检测放大器还包括具有连接到第一和第二检测晶体管的相应漏极的第一端子的第一和第二负载器件以及连接到第一和第二检测晶体管的相应漏极的第一和第二输入端的锁存器。该放大器还包括响应于使能信号的使能装置，并且具有连接到第一和第二负载装置的第二端子的第一端子和锁存器的第一输出端。

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