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131. 发明授权

US07616028B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US07616028B2
公开(公告)日：2009-11-10
申请号：US11942665
申请日：2007-11-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

132. 发明申请

US20090147579A1 NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES 有权
标题翻译：非易失性存储器系统和包括页面读取和/或配置功能的方法
公开(公告)号：US20090147579A1
公开(公告)日：2009-06-11
申请号：US12275191
申请日：2008-11-20
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/04 , G11C17/00 , G11C16/06 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

133. 发明申请

US20080080235A1 Power line compensation for flash memory sense amplifiers 有权
标题翻译：闪存读出放大器的电源线补偿
公开(公告)号：US20080080235A1
公开(公告)日：2008-04-03
申请号：US11528748
申请日：2006-09-27
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06 , G11C7/10
CPC分类号： G11C7/062 , G11C5/147 , G11C7/02 , G11C7/06 , G11C7/065 , G11C7/067 , G11C11/4091 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2207/063 , G11C2211/5645
摘要： In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
摘要翻译：一方面，本发明涉及一种用于补偿多电平存储器的读出放大器中的功率电平变化的存储器系统。例如，可以采用补偿电路来补偿提供给多电平存储器读出放大器的功率的电流或电压变化。作为另一示例，可以通过向电源施加偏置电压来实现补偿。另一个例子是配置有改进的输入共模电压范围的读出放大器。这样的读出放大器可以是两对和三对读出放大器。本发明的其它示例包括更简化的读出放大器配置和具有减小的漏电流的读出放大器。

134. 发明授权

US07184345B2 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统的高速和高精度感测
公开(公告)号：US07184345B2
公开(公告)日：2007-02-27
申请号：US11283195
申请日：2005-11-18
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

135. 发明授权

US07158431B2 Single transistor sensing and double transistor sensing for flash memory 有权
标题翻译：用于闪存的单晶体管感测和双晶体管感测
公开(公告)号：US07158431B2
公开(公告)日：2007-01-02
申请号：US11092166
申请日：2005-03-28
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C7/06
CPC分类号： G11C7/067 , G11C7/06 , G11C7/062 , G11C7/12 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.
摘要翻译：单个感测晶体管被选择性地二极管连接到感测线，该感测线耦合到参考单元和数据单元，以通过打开开关来断开感测晶体管的二极管连接来在感测晶体管的栅极上存储参考电流或漏电流。其他感测系统可以使用两个晶体管并且可以存储泄漏电流。包含电容自动归零的感应系统。感测系统可以包括动态差分电流差分放大器。

136. 发明授权

US07061295B2 Ring oscillator for digital multilevel non-volatile memory 有权
标题翻译：用于数字多电平非易失性存储器的环形振荡器
公开(公告)号：US07061295B2
公开(公告)日：2006-06-13
申请号：US10991301
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G06F1/04
CPC分类号： H02M3/07 , G11C16/30
摘要： An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.
摘要翻译：可用于非易失性存储器的高压发生和调节系统中的振荡器。该系统可以包括可以具有至少一个泵和振荡器的电荷泵。在一个方面，振荡器向泵提供时钟信号。可以禁用振荡器的输出而不关闭时钟产生。振荡器可以是环形振荡器。在一个方面，环形振荡器和输出级可以包括具有耦合到反相器的输出的电容器的反相器。在一个方面，环形振荡器中的电容器与输出级中的电容器的比率决定了两个时钟信号之间的相移。在另一方面，电容器的电容是相同的，并且施加环形振荡器的偏置，并且输出级被无线电以调节两个时钟信号之间的相位。

137. 发明授权

US07038538B2 Folded cascode high voltage operational amplifier with class AB source follower output stage 有权
公开(公告)号：US07038538B2
公开(公告)日：2006-05-02
申请号：US10376989
申请日：2003-02-26
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
IPC分类号： H03G5/16
CPC分类号： H03F3/45192
摘要： An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement. A local power supply pre-filter provides a filtered local high voltage to the differential input stage and stages that provide the fixed and adaptive voltage bias signals.

138. 发明授权

US06975539B2 Digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统
公开(公告)号：US06975539B2
公开(公告)日：2005-12-13
申请号：US10317375
申请日：2002-12-11
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C11/56 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/00 , G11C16/06
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (
摘要翻译：数字多位非易失性存储器集成系统包括自动调零多级感测。一个阶段可以提供自动归零的局部感测。另一个阶段可以提供自动归零的全局感测。扭转位线可用于阵列布置。段参考可用于每个段。系统可以使用电流感测一或两步二进制搜索来读取数据单元。该系统可以使用反向电压模式或反向电流模式感测。该系统可以不使用当前的多电平感测。该系统可以使用存储器单元复制感测。该系统可以使用动态感测。系统可以使用内置的字节冗余。描述了能够进行亚伏特（<< 1V）感测的感测放大器。

139. 发明授权

US06906379B2 Semiconductor memory array of floating gate memory cells with buried floating gate 有权
标题翻译：具有埋置浮栅的浮动存储单元半导体存储器阵列
公开(公告)号：US06906379B2
公开(公告)日：2005-06-14
申请号：US10653015
申请日：2003-08-28
申请人： Bomy Chen , Dana Lee , Hieu Van Tran
发明人： Bomy Chen , Dana Lee , Hieu Van Tran
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7885
摘要： An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.
摘要翻译：一种浮动栅极存储单元的阵列及其制造方法，其中每对存储单元包括形成在半导体衬底的表面中的一对沟槽，其中衬底的条带设置在其间，源区域形成在衬底条，一对漏极区，一对沟道区，每个沟道区各自在源极区和漏极区之一之间延伸;一对浮置栅极，分别设置在一个沟槽中，以及一对控制栅极。每个通道区域具有设置在衬底条中并沿其中一个沟槽延伸的第一部分，在一个沟槽下面延伸的第二部分，沿该沟槽延伸的第三部分，以及沿衬底表面延伸的第四部分的控制门。

140. 发明授权

US06885600B2 Differential sense amplifier for multilevel non-volatile memory 有权
标题翻译：差分放大器用于多电平非易失性存储器
公开(公告)号：US06885600B2
公开(公告)日：2005-04-26
申请号：US10241266
申请日：2002-09-10
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C17/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/065 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

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