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131. 发明授权

US06967524B2 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
标题翻译：用于数字多级非易失性存储器的高压发生和调节系统
公开(公告)号：US06967524B2
公开(公告)日：2005-11-22
申请号：US10990786
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/30 , H02M3/07 , G05F1/10
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.
摘要翻译：高压发生器提供具有不同调节电压电平的高电压信号。电荷泵产生高电压，并且包括具有上电辅助二极管的正交相位正向和反向Vt消除高电压自偏压电荷泵。高压串联调节器产生高电压电平，并包括压摆率增强和可调二极管调节。嵌套回路调节器消除了分流调节。

132. 发明授权

US06504754B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06504754B2
公开(公告)日：2003-01-07
申请号：US09898582
申请日：2001-07-02
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

133. 发明授权

US06396742B1 Testing of multilevel semiconductor memory 有权
标题翻译：多层半导体存储器测试
公开(公告)号：US06396742B1
公开(公告)日：2002-05-28
申请号：US09627917
申请日：2000-07-28
申请人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
发明人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C11/56 , G11C11/5621 , G11C29/50 , G11C2029/5004
摘要： In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
摘要翻译：根据本发明的实施例，一种用于测试多电平存储器的方法包括：执行擦除操作以将多个存储单元置于擦除状态; 将所述多个单元的组中的每个单元的状态编程为在第一电压范围内; 如果所述单元组中的一个或多个单元格中的每一个的状态未被验证到所述第一电压范围内，则至少将所述一个或多个单元识别为故障; 并且如果所述单元组中的每个单元的状态验证为在所述第一电压范围内：施加预定数量的编程脉冲以进一步将所述单元组中的每个单元的状态编程到第二电压范围内; 以及验证所述单元组中的每个单元的状态是否被编程超过所述第二电压范围。

134. 发明授权

US5995413A Trimbit circuit for flash memory integrated circuits 失效
公开(公告)号：US5995413A
公开(公告)日：1999-11-30
申请号：US245119
申请日：1999-02-04
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

135. 发明授权

US5933370A Trimbit circuit for flash memory 失效
标题翻译：闪存集成电路的Trimbit电路
公开(公告)号：US5933370A
公开(公告)日：1999-08-03
申请号：US5074
申请日：1998-01-09
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.
摘要翻译：描述了闪存集成电路的三段电路。 trimbit电路用于存储闪存阵列中不良行和/或列的地址。此外，trimbit电路用于存储集成电路中的可修整电路的三角形，即电压基准，精密振荡器等。本发明包括一排闪存微调单元和微调单元差分放大器电路。微调单元差分放大器电路可以将三位组串行移位到锁存器中，并且串行地移出三位符，而不必对闪存微调单元进行编程。可以通过高电压缓冲区对三角形的最终设置进行编程。还包括不重叠的时钟发生器和附加逻辑来控制电路。

136. 发明授权

US5909393A Method and apparatus for reading analog values stored in floating gate NAND structures 失效
标题翻译：用于读取存储在浮动栅极NAND结构中的模拟值的方法和装置
公开(公告)号：US5909393A
公开(公告)日：1999-06-01
申请号：US887108
申请日：1997-07-01
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

137. 发明授权

US08804429B2 Non-volatile memory device and a method of programming such device 有权
标题翻译：非易失性存储器件和这种器件的编程方法
公开(公告)号：US08804429B2
公开(公告)日：2014-08-12
申请号：US13315213
申请日：2011-12-08
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/10 , G11C7/00 , G11C7/22 , G11C16/26 , G11C16/28 , G11C2207/2263 , G11C2211/5647 , H01L27/11517
摘要： A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.
摘要翻译：非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。阵列的每个存储单元都由来自电荷泵的编程电流编程。非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。指示器存储单元与每单位的非易失性存储单元相关联。编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

138. 发明授权

US08773934B2 Power line compensation for flash memory sense amplifiers 有权
标题翻译：闪存读出放大器的电源线补偿
公开(公告)号：US08773934B2
公开(公告)日：2014-07-08
申请号：US11528748
申请日：2006-09-27
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C7/02 , G11C7/06 , G11C11/4091
CPC分类号： G11C7/062 , G11C5/147 , G11C7/02 , G11C7/06 , G11C7/065 , G11C7/067 , G11C11/4091 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2207/063 , G11C2211/5645
摘要： In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
摘要翻译：一方面，本发明涉及一种用于补偿多电平存储器的读出放大器中的功率电平变化的存储器系统。例如，可以采用补偿电路来补偿提供给多电平存储器读出放大器的功率的电流或电压变化。作为另一示例，可以通过向电源施加偏置电压来实现补偿。另一个例子是配置有改进的输入共模电压范围的读出放大器。这样的读出放大器可以是两对和三对读出放大器。本发明的其它示例包括更简化的读出放大器配置和具有减小的漏电流的读出放大器。

139. 发明申请

US20130187707A1 Charge Pump Systems and Methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20130187707A1
公开(公告)日：2013-07-25
申请号：US13726522
申请日：2012-12-24
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

140. 发明申请

US20130107632A1 Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving 有权
标题翻译：具有省电的混合电压非易失性存储器集成电路
公开(公告)号：US20130107632A1
公开(公告)日：2013-05-02
申请号：US13286969
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

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