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1. 发明授权

US06519180B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06519180B2
公开(公告)日：2003-02-11
申请号：US09929370
申请日：2001-08-13
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

2. 发明授权

US07035151B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US07035151B2
公开(公告)日：2006-04-25
申请号：US10868614
申请日：2004-06-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

3. 发明授权

US06504754B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06504754B2
公开(公告)日：2003-01-07
申请号：US09898582
申请日：2001-07-02
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

4. 发明授权

US06396742B1 Testing of multilevel semiconductor memory 有权
标题翻译：多层半导体存储器测试
公开(公告)号：US06396742B1
公开(公告)日：2002-05-28
申请号：US09627917
申请日：2000-07-28
申请人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
发明人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C11/56 , G11C11/5621 , G11C29/50 , G11C2029/5004
摘要： In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
摘要翻译：根据本发明的实施例，一种用于测试多电平存储器的方法包括：执行擦除操作以将多个存储单元置于擦除状态; 将所述多个单元的组中的每个单元的状态编程为在第一电压范围内; 如果所述单元组中的一个或多个单元格中的每一个的状态未被验证到所述第一电压范围内，则至少将所述一个或多个单元识别为故障; 并且如果所述单元组中的每个单元的状态验证为在所述第一电压范围内：施加预定数量的编程脉冲以进一步将所述单元组中的每个单元的状态编程到第二电压范围内; 以及验证所述单元组中的每个单元的状态是否被编程超过所述第二电压范围。

5. 发明授权

US06590825B2 Non-volatile flash fuse element 有权
标题翻译：非易失性闪存保险丝元件
公开(公告)号：US06590825B2
公开(公告)日：2003-07-08
申请号：US10002036
申请日：2001-11-01
申请人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
发明人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C16/04 , G11C16/0441 , G11C29/02 , G11C29/50
摘要： A non-volatile flash fuse element and an array of such elements include fuses coupled to the input of a latch arranged as a differential comparator for constant current differential sensing. The fuse element includes a margining circuit that provides differential mass fuse margining. The margining circuit also allows the fuses to be stressed and screened. The fuse elements also provide constant current parallel programming.
摘要翻译：非易失性闪存熔丝元件和这种元件的阵列包括耦合到作为用于恒定电流差动感测的差分比较器的锁存器的输入的熔丝。保险丝元件包括提供差分质量保险丝边缘的边缘电路。保险丝电路还允许保险丝受到压力和屏蔽。熔丝元件还提供恒流并行编程。

6. 发明授权

US06992937B2 Column redundancy for digital multilevel nonvolatile memory 有权
标题翻译：数字多级非易失性存储器的列冗余
公开(公告)号：US06992937B2
公开(公告)日：2006-01-31
申请号：US10628979
申请日：2003-07-28
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/5621 , G11C16/04 , G11C29/027 , G11C29/50004 , G11C29/82 , G11C2029/0409
摘要： A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.
摘要翻译：数字多电平位存储器阵列系统包括常规存储器阵列和冗余存储器阵列。常规y驱动器对应于每个存储器阵列以将内容读取或写入多级位存储器单元，并将读取的单元内容与参考电压电平进行比较，以确定存储在相应存储器单元中的数据。类似的功能由冗余的y驱动电路执行，用于冗余存储器阵列。在验证存储单元的内容期间，如果读取电压超出参考电压电平的一定余量要求，则实时生成信号，以便不输出来自不良y驱动器的数据和数据从对应于冗余存储器阵列的冗余y驱动器读出。存储器阵列系统还可以包括分数多级冗余。

7. 发明授权

US06751118B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
标题翻译：数字多层非易失性存储器集成电路系统的阵列架构和操作方法
公开(公告)号：US06751118B2
公开(公告)日：2004-06-15
申请号：US09929542
申请日：2001-08-13
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： C16
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
摘要翻译：内存阵列架构和操作方法适用于超高密度千兆比特的多级非易失性存储器集成电路系统。阵列架构和操作方法包括：（1）禁止和选择分割方案; （2）一种多级存储器解码方案，其包括电源解码解码方案，馈通到存储器解码方案，馈通到驱动器解码方案和获胜者采用所有开尔文存储器解码方案; （3）不变总计程序方案; （4）包括快速慢速和2级斜坡速率控制编程; 以及参考系统方法和装置，其包括位置线性参考系，位置几何参考系和几何补偿参考系。该装置和方法能够实现多级编程，读取和保留。

8. 发明授权

US06282145B1 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
标题翻译：数字多层非易失性存储器集成电路系统的阵列架构和操作方法
公开(公告)号：US06282145B1
公开(公告)日：2001-08-28
申请号：US09231928
申请日：1999-01-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C800
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
摘要翻译：内存阵列架构和操作方法适用于超高密度千兆比特的多级非易失性存储器集成电路系统。阵列架构和操作方法包括：（1）禁止和选择分割方案; （2）一种多级存储器解码方案，其包括电源解码解码方案，馈通到存储器解码方案，馈通到驱动器解码方案和获胜者采用所有开尔文存储器解码方案; （3）不变总计程序方案; （4）包括快速慢速和2级斜坡速率控制编程; 以及参考系统方法和装置，其包括位置线性参考系，位置几何参考系和几何补偿参考系。该装置和方法能够实现多级编程，读取和保留。

9. 发明授权

US07471581B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
标题翻译：用于多电平数字非易失性存储器的宽动态范围和高速电压模式感测
公开(公告)号：US07471581B2
公开(公告)日：2008-12-30
申请号：US11726913
申请日：2007-03-22
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

10. 发明授权

US06865099B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
标题翻译：用于多电平数字非易失性存储器的宽动态范围和高速电压模式感测
公开(公告)号：US06865099B2
公开(公告)日：2005-03-08
申请号：US10211886
申请日：2002-08-01
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C11/56 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/00 , G11C5/06
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

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