会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Trimbit circuit for flash memory
    • 闪存集成电路的Trimbit电路
    • US5933370A
    • 1999-08-03
    • US5074
    • 1998-01-09
    • Peter HolzmannJames Brennan, Jr.Anthony DunneHieu Van Tran
    • Peter HolzmannJames Brennan, Jr.Anthony DunneHieu Van Tran
    • G11C16/06G11C29/00G11C29/04G11C16/04
    • G11C29/789
    • A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.
    • 描述了闪存集成电路的三段电路。 trimbit电路用于存储闪存阵列中不良行和/或列的地址。 此外,trimbit电路用于存储集成电路中的可修整电路的三角形,即电压基准,精密振荡器等。本发明包括一排闪存微调单元和微调单元差分放大器电路。 微调单元差分放大器电路可以将三位组串行移位到锁存器中,并且串行地移出三位符,而不必对闪存微调单元进行编程。 可以通过高电压缓冲区对三角形的最终设置进行编程。 还包括不重叠的时钟发生器和附加逻辑来控制电路。
    • 8. 发明授权
    • High output swing operational amplifier using low voltage devices
    • 高输出摆幅运算放大器采用低压器件
    • US6018267A
    • 2000-01-25
    • US37233
    • 1998-03-10
    • Hieu Van TranAnthony Dunne
    • Hieu Van TranAnthony Dunne
    • H03F3/30H03F3/45
    • H03F3/3023H03F3/45192H03F2200/153H03F2203/30009H03F2203/30015H03F2203/30033H03F2203/30036H03F2203/30084H03F2203/30117H03F2203/45396H03F2203/45398H03F2203/45508H03F2203/45626
    • A power efficient high output swing operational ("HOOP") amplifier for integrated circuit analog signal processing is described. The operational amplifier includes a differential input stage and an output stage. The differential input stage is powered by a regular power supply while the output stage is powered by a voltage multiplier which results in a high voltage output swing without sinking significant power from the voltage multiplier. The high output voltage (e.g., 23 volts) is achieved using low voltage MOS devices. An output isolation technique is utilized to prevent possible latchup and contention. The operational amplifier also features a bias boot scheme to achieve a faster settling time from power up. In addition, the present invention provides realization of frequency compensation with highest possible breakdown and reduced noise coupling. A bias arrangement between input and output stages of the operational amplifier is used to further help reduce the power drawn from the voltage multiplier and decrease the settling time.
    • 描述了用于集成电路模拟信号处理的功率有效的高输出摆幅操作(“HOOP”)放大器。 运算放大器包括差分输入级和输出级。 差分输入级由常规电源供电,而输出级由电压倍增器供电,导致高电压输出摆幅,而不会从电压倍增器吸收大量功率。 使用低电压MOS器件实现高输出电压(例如,23伏特)。 使用输出隔离技术来防止可能的闭锁和争用。 运算放大器还具有偏置引导方案,以实现从上电更快的建立时间。 此外,本发明提供了具有最高可能击穿和降低的噪声耦合的频率补偿的实现。 使用运算放大器的输入和输出级之间的偏置布置来进一步帮助降低从电压倍增器引出的功率并降低建立时间。
    • 9. 发明授权
    • Analog signal recording and playback integrated circuit and message
management system
    • 模拟信号记录和回放集成电路和消息管理系统
    • US5828592A
    • 1998-10-27
    • US819665
    • 1997-03-12
    • Hieu Van TranNataraj S. BindiganavaleAnthony DunneBoyce W. Jarrett
    • Hieu Van TranNataraj S. BindiganavaleAnthony DunneBoyce W. Jarrett
    • G11C27/00G11C29/44G11C11/34
    • G11C27/005G11C29/44
    • An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes redundancy to increase production yield. It also utilizes a high speed test mode to reduce production testing time.
    • 公开了一种使用非易失性模拟信号记录和重放的消息管理的装置和方法。 该器件是具有接口电路的集成电路,用作微控制器或基于微处理器的系统的外围设备。 集成电路配有差分模拟输入,自动衰减以提高信号质量,滤波器,固定参考,包括带隙参考,微调,存储阵列,多个闭环采样和保持电路,列设备,行解码器,地址计数器,主器件 振荡器,芯片功能定时电路,以及串行外设接口(SPI)和单芯片上的电路。 集成电路通过SPI与主机微控制器连接。 主机微控制器可以通过SPI向集成电路发送多个命令,以实现高效的消息管理。 这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。 该系统利用冗余来提高产量。 它还利用高速测试模式来减少生产测试时间。
    • 10. 发明授权
    • Non-volatile memory device and a method of operating same
    • 非易失性存储器件及其操作方法
    • US08811093B2
    • 2014-08-19
    • US13419269
    • 2012-03-13
    • Hieu Van TranHung Quoc NguyenNhan Do
    • Hieu Van TranHung Quoc NguyenNhan Do
    • G11C16/04
    • G11C16/04G11C16/0425G11C16/06G11C16/12G11C16/30G11C16/3418
    • An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
    • 在第一导电类型的半导体衬底中的非易失性存储单元阵列。 每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域,其间具有沟道区域。 字线重叠在通道区域的一部分上,与第一区域相邻,并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的另一部分,并且与第一部分和第二区域相邻。 耦合栅极覆盖浮栅。 擦除门覆盖第二区域。 位线连接到第一区域。 负电荷泵电路产生负电压。 控制电路响应于接收到命令信号而产生多个控制信号,并将负电压施加到未选择存储单元的字线。