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121. 发明申请

US20060249837A1 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US20060249837A1
公开(公告)日：2006-11-09
申请号：US11482308
申请日：2006-07-07
申请人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
发明人： Paul Farrar , Leonard Forbes , Kie Ahn , Joseph Geusic , Arup Bhattacharyya , Alan Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

122. 发明申请

US20060249777A1 Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces 失效
标题翻译：具有微粗糙半导体表面的沟槽电容器的装置，系统和方法
公开(公告)号：US20060249777A1
公开(公告)日：2006-11-09
申请号：US11484541
申请日：2006-07-11
申请人： Leonard Forbes , Joseph Geusic , Kie Ahn
发明人： Leonard Forbes , Joseph Geusic , Kie Ahn
IPC分类号： H01L29/94
CPC分类号： H01L27/10861 , H01L28/82 , H01L29/66181
摘要： Some embodiments of the invention include a memory cell having a vertical transistor and a trench capacitor. The trench capacitor includes a capacitor plate with a roughened surface for increased surface area. Other embodiments are described and claims.
摘要翻译：本发明的一些实施例包括具有垂直晶体管和沟槽电容器的存储单元。沟槽电容器包括具有粗糙表面的电容器板，用于增加表面积。其他实施例被描述和权利要求。

123. 发明申请

US20060234450A1 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers 有权
公开(公告)号：US20060234450A1
公开(公告)日：2006-10-19
申请号：US11471007
申请日：2006-06-20
申请人： Leonard Forbes , Jerome Eldridge , Kie Ahn
发明人： Leonard Forbes , Jerome Eldridge , Kie Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , G11C16/0416 , H01L27/115 , H01L29/51 , H01L29/511 , H01L29/7881 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator.

124. 发明申请

US20060208309A1 Non-planar flash memory having shielding between floating gates 有权
标题翻译：浮动栅极之间具有屏蔽的非平面闪存
公开(公告)号：US20060208309A1
公开(公告)日：2006-09-21
申请号：US11436247
申请日：2006-05-18
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. A second set of trenches, perpendicular to the first set, is formed to separate columns of the array. Word lines are formed along rows of the array. The word lines are formed into the second set of trenches in order to shield adjacent floating gates. Metal shields are formed in the first set of trenches along the rows and between floating gates on the pillars.
摘要翻译：在阵列的第一列中的柱上形成第一多个存储单元。第二组多个存储单元形成在同一列中的第一组沟槽中。第二多个存储器单元通过其源极/漏极区域的串联连接耦合到第一多个存储器单元。垂直于第一组的第二组沟槽形成为分离阵列的列。字线沿数组的行形成。字线形成第二组沟槽，以屏蔽相邻的浮动栅极。沿着行的第一组沟槽和柱上的浮动浇口之间形成金属屏蔽。

125. 发明申请

US20060199338A1 ATOMIC LAYER DEPOSITION OF METAL OXIDE AND/OR LOW ASYMMETRICAL TUNNEL BARRIER INTERPOLY INSULATORS 有权
标题翻译：金属氧化物和/或低不对称隧道式隔离绝缘子的原子层沉积
公开(公告)号：US20060199338A1
公开(公告)日：2006-09-07
申请号：US11380599
申请日：2006-04-27
申请人： Jerome Eldridge , Kie Ahn , Leonard Forbes
发明人： Jerome Eldridge , Kie Ahn , Leonard Forbes
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/66825 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
摘要翻译：提供了具有不对称低隧道势垒隔离绝缘子的可编程阵列型逻辑和/或存储器件的结构和方法。可编程阵列型逻辑和/或存储器件包括具有第一源极/漏极区域和由衬底中的沟道区域分开的第二源极/漏极区域的非易失性存储器。与沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过由原子层沉积物形成的不对称的低隧道势垒隔间绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al 2 O 3 O 3，Ta 2 O 3的金属氧化物绝缘体， 5，TiO 2，ZrO 2，Nb 2 O 5，SrBi 2 TaTiO 3，PbTiO 3 3和PbZrO 3 3，3， / SUB>。

126. 发明申请

US20060189154A1 Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics 有权
标题翻译： Hf3N4 / HfO2薄膜的原子层沉积作为栅极电介质
公开(公告)号：US20060189154A1
公开(公告)日：2006-08-24
申请号：US11063717
申请日：2005-02-23
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/336
CPC分类号： H01L21/0228 , C23C16/34 , C23C16/405 , C23C16/45529 , H01L21/02181 , H01L21/022 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/3143 , H01L21/318 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf3N4) and hafnium oxide (HfO2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using precursor chemicals, followed by depositing hafnium nitride using precursor chemicals, and repeating to form the laminate structure. Alternatively, the hafnium nitride may be deposited first followed by the hafnium nitride. Such a dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric in a DRAM, or a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current when compared to an electrically equivalent thickness of silicon dioxide.
摘要翻译：使用原子层沉积（ALD）来形成氮化铪（Hf 3 N 4 N 4）和氧化铪（HfO 2 N 2）的电介质层，）和制造这种组合栅极和电介质层的方法产生用于各种电子器件的可靠结构。形成电介质结构包括使用前体化学品沉积氧化铪，然后使用前体化学品沉积铪氮化物，并重复形成层压结构。或者，首先可以沉积氮化铪，然后氮化铪。这样的电介质层可以用作MOSFET的栅极绝缘体，DRAM中的电容器电介质或闪存中的隧道栅极绝缘体，因为膜的高介电常数（高k）提供了更薄的功能并且与电二氧化硅的电等效厚度相比，由于漏电流减小。

127. 发明申请

US20060177975A1 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics 有权
公开(公告)号：US20060177975A1
公开(公告)日：2006-08-10
申请号：US11055380
申请日：2005-02-10
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/8234
CPC分类号： H01L21/28194 , C23C16/40 , C23C16/45529 , H01L21/02178 , H01L21/02192 , H01L21/022 , H01L21/0228 , H01L21/3142 , H01L21/31604 , H01L21/3162 , H01L29/513 , H01L29/517 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

128. 发明申请

US20060176645A1 Atomic layer deposition of Dy doped HfO2 films as gate dielectrics 有权
标题翻译：作为栅极电介质的Dy掺杂HfO 2膜的原子层沉积
公开(公告)号：US20060176645A1
公开(公告)日：2006-08-10
申请号：US11053577
申请日：2005-02-08
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01G4/06
CPC分类号： H01L21/02181 , C23C16/405 , C23C16/45529 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.
摘要翻译：使用原子层沉积（ALD）形成掺杂有镝（Dy）的氧化铪（HfO 2 N 2）的介电层和制造这种组合栅极和电介质层的方法产生可靠的结构用于各种电子设备。形成电介质结构包括使用前体化学品将原子层沉积物沉积到衬底表面上，然后使用前体化学品将氧化镝沉积到衬底上，并重复形成薄的层压结构。镝掺杂氧化铪的电介质层可用作MOSFET的栅极绝缘体，作为DRAM中的电容器电介质，作为闪存中的隧道栅极绝缘体或NROM器件中的电介质，因为高介电常数（高k）的薄膜提供更薄的二氧化硅膜的功能，并且由于优化了镝掺杂的百分比时介电层的漏电流减小，从而提高记忆功能。

129. 发明申请

US20060131702A1 Novel transmission lines for CMOS integrated circuits 有权
公开(公告)号：US20060131702A1
公开(公告)日：2006-06-22
申请号：US11340089
申请日：2006-01-26
申请人： Leonard Forbes , Eugene Cloud , Kie Ahn
发明人： Leonard Forbes , Eugene Cloud , Kie Ahn
IPC分类号： H01L29/40
CPC分类号： H01L23/5225 , H01L2223/6627 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

130. 发明申请

US20060131684A1 Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same 有权
公开(公告)号：US20060131684A1
公开(公告)日：2006-06-22
申请号：US11342940
申请日：2006-01-30
申请人： Joseph Geusic , Kie Ahn , Leonard Forbes
发明人： Joseph Geusic , Kie Ahn , Leonard Forbes
IPC分类号： H01L31/0232
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/42 , G02B6/43
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

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