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121. 发明授权

US06645789B2 On chip alpha-particle detector 失效
公开(公告)号：US06645789B2
公开(公告)日：2003-11-11
申请号：US10246136
申请日：2002-09-18
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2100
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

122. 发明授权

US06580293B1 Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
标题翻译：身体接触和双门接触差分逻辑电路及其操作方法
公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译：设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

123. 发明授权

US06548338B2 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06548338B2
公开(公告)日：2003-04-15
申请号：US09764504
申请日：2001-01-17
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

124. 发明授权

US06501294B2 Neuron circuit 有权
标题翻译：神经元电路
公开(公告)号：US06501294B2
公开(公告)日：2002-12-31
申请号：US09842736
申请日：2001-04-26
申请人： Kerry Bernstein , Norman Jay Rohrer
发明人： Kerry Bernstein , Norman Jay Rohrer
IPC分类号： H03K1923
CPC分类号： G06N3/063
摘要： A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.
摘要翻译：公开了可以用作在集成电路中实现的神经网络的构建块的神经元电路。神经元电路包括突触电路块和神经元体电路块。突触电路块具有三个晶体管，三个晶体管中的一个的主体由加权输入控制。神经元体电路块包括电流镜电路，加法电路和反相器电路。神经元体电路耦合到突触电路块以产生输出脉冲。

125. 发明授权

US06433587B1 SOI CMOS dynamic circuits having threshold voltage control 失效
标题翻译：具有阈值电压控制的SOI CMOS动态电路
公开(公告)号：US06433587B1
公开(公告)日：2002-08-13
申请号：US09528207
申请日：2000-03-17
申请人： Fariborz Assaderaghi , Kerry Bernstein , Michael J. Hargrove , Norman J. Rohrer , Peter Smeys
发明人： Fariborz Assaderaghi , Kerry Bernstein , Michael J. Hargrove , Norman J. Rohrer , Peter Smeys
IPC分类号： H03K19096
CPC分类号： H03K19/00361 , H03K19/096
摘要： A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.
摘要翻译：用于维持在动态CMOS电路中实现的晶体管的阈值电压的电路。多个晶体管具有连接在动态CMOS电路中的晶体管的主体触点之间的源极漏极连接以及恒定的电压电位。当在预充电阶段中操作动态CMOS电路时，每个CMOS电路晶体管的主体保持在恒定的电压电位。在评估阶段，允许身体电位浮动到其预充电状态。在预充电阶段期间建立的初始参考电平电压将晶体管栅极 - 源极阈值电压保持在恒定值，消除伴随身体电位变化的双极效应和历史效应。

126. 发明授权

US06433372B1 Dense multi-gated device design 失效
标题翻译：密集的多门控设备设计
公开(公告)号：US06433372B1
公开(公告)日：2002-08-13
申请号：US09527863
申请日：2000-03-17
申请人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
发明人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H01L2972
CPC分类号： H01L29/66484
摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.
摘要翻译：具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。

127. 发明授权

US06236103B1 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06236103B1
公开(公告)日：2001-05-22
申请号：US09283828
申请日：1999-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

128. 发明授权

US4727267A Clocked buffer circuit 失效
标题翻译：时钟缓冲电路
公开(公告)号：US4727267A
公开(公告)日：1988-02-23
申请号：US062036
申请日：1987-06-15
申请人： Kerry Bernstein
发明人： Kerry Bernstein
IPC分类号： G11C7/00 , G11C8/16 , G11C8/18 , G11C8/20 , H03K19/094
CPC分类号： G11C8/20 , G11C7/00 , G11C8/16 , G11C8/18
摘要： The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the applied clock signal control the decode circuit, but the output of the latch will also control the decode circuit thus assuring the output of the decode circuit becomes latched into the set by the input clock signal.
摘要翻译：本发明特别涉及一种改进的时钟缓冲电路，其将对输入信号进行时钟，解码，重复和反转。时钟缓冲电路使用与解码电路耦合的时钟锁存器，使得所施加的时钟信号不仅控制解码电路，而且锁存器的输出也将控制解码电路，从而确保解码电路的输出被锁存由输入时钟信号设定。

129. 发明授权

US08569803B2 BEOL compatible FET structrure 有权
标题翻译： BEOL兼容FET结构
公开(公告)号：US08569803B2
公开(公告)日：2013-10-29
申请号：US13572742
申请日：2012-08-13
申请人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
发明人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
IPC分类号： H01L29/76
CPC分类号： H01L23/5226 , H01L23/53271 , H01L27/124 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
摘要翻译：本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

130. 发明授权

US08513791B2 Compact multi-port CAM cell implemented in 3D vertical integration 失效
标题翻译：紧凑型多端口CAM单元在3D垂直整合中实现
公开(公告)号：US08513791B2
公开(公告)日：2013-08-20
申请号：US11750631
申请日：2007-05-18
申请人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
发明人： Robert J. Bucki , Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Eric Robinson
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C15/00 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2224/24226 , H01L2224/80896 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.
摘要翻译：提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件。通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。

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