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121. 发明授权

US09342258B2 Integrated circuit device and method for providing data access control 有权
标题翻译：用于提供数据访问控制的集成电路装置和方法
公开(公告)号：US09342258B2
公开(公告)日：2016-05-17
申请号：US14238495
申请日：2011-09-01
申请人： Manfred Thanner , Nancy Amedeo , Stephan Mueller , Anthony Reipold
发明人： Manfred Thanner , Nancy Amedeo , Stephan Mueller , Anthony Reipold
IPC分类号： G06F3/00 , G06F3/06 , G06F12/08 , G06F13/16
CPC分类号： G06F3/0656 , G06F3/0611 , G06F3/0671 , G06F12/0862 , G06F13/1673 , G06F2212/6022
摘要： An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.
摘要翻译：一种集成电路装置，包括至少一个存储器接口模块，其布置成可操作地耦合在数据处理系统内的至少一个数据存储设备和多个主设备之间。所述至少一个存储器接口模块包括多个缓冲器和至少一个数据访问控制模块。所述至少一个数据访问控制模块被布置成响应于包括主设备标识符的接收到的存储器访问请求从所述至少一个数据存储设备提取数据，至少部分地基于所述主设备标识符来选择至少一个缓冲器所接收的访问请求，并将获取的数据加载到所选择的至少一个缓冲器中。

122. 发明申请

US20160134273A1 EMITTER FOLLOWER BUFFER WITH REVERSE-BIAS PROTECTION 有权
标题翻译：具有反向偏置保护功能的发动机保险杠
公开(公告)号：US20160134273A1
公开(公告)日：2016-05-12
申请号：US14899130
申请日：2013-07-03
申请人： Bernhard DEHLINK , Cristian PAVAO-MOREIRA
发明人： BERNHARD DEHLINK , CRISTIAN PAVAO-MOREIRA
IPC分类号： H03K17/16
CPC分类号： H03K17/165 , H03F1/52 , H03F3/189 , H03F3/50 , H03F2200/294
摘要： The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor.
摘要翻译：本发明涉及一种用于接收机设备的缓冲电路，包括跨导级和与器件的其它通道的输出级并联的输出级。跨导级的输出端连接到输出级的双极晶体管的基极。开关连接在双极晶体管的基极和双极晶体管的发射极之间。控制器被设置为将缓冲电路从关断模式切换到接通模式并返回。在关断模式下，开关接通，以连接双极晶体管的基极和发射极。

123. 发明申请

US20160132332A1 SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION 审中-公开
标题翻译：信号处理装置和执行位扩展操作的方法
公开(公告)号：US20160132332A1
公开(公告)日：2016-05-12
申请号：US14898353
申请日：2013-06-18
申请人： Roy GLASNER , Fabrice AIDAN , Aviram AMIR , Noam ESHEL-GOLDMAN , Avi GAL , Ilia MOSKOVICH
发明人： ROY GLASNER , FABRICE AIDAN , AMIR AVIRAM , NOAM ESHEL-GOLDMAN , AVI GAL , ILIA MOSKOVICH
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30098
摘要： A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.
摘要翻译：一种信号处理装置，包括至少一个控制单元，其被配置为接收至少一个位扩展指令，对所接收的至少一个位扩展指令进行解码，以及根据接收的至少一个位扩展来输出至少一个控制信号指令。所述信号处理设备还包括至少一个执行单元组件，被布置为接收包括至少一个要扩展的数据位的至少一个源寄存器值，从位于偏移位置的至少一个源寄存器值提取至少一个数据位根据至少一个控制信号，将至少一个提取的数据位扩展为至少一个多位数据类型，并将至少一个多位数据类型输出到至少一个目标寄存器。

124. 发明申请

US20160132070A1 OSCILLATOR CIRCUIT AND METHOD OF GENERATING A CLOCK SIGNAL 有权
标题翻译：振荡器电路和产生时钟信号的方法
公开(公告)号：US20160132070A1
公开(公告)日：2016-05-12
申请号：US14899170
申请日：2013-07-04
申请人： Hubert BODE , Dirk WENDEL
发明人： HUBERT BODE , DIRK WENDEL
IPC分类号： G06F1/08 , H03K3/023
CPC分类号： G06F1/08 , H03K3/023 , H03K3/0231
摘要： An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
摘要翻译：一种振荡器电路，包括用于产生时钟信号的触发器和用于将参考电压与在第一电容器的第一周期期间充电的第一电容器两端的电压进行比较的两个比较器，以及跨越第二电容器的电压在时钟信号的第二周期期间被充电提供了用于消除任一比较器中任何偏移的影响的装置。这是通过在输出频率的每个周期反转比较器的输入来实现的。因此，将在一个周期上增加时钟周期的比较器中的偏移将使下一个周期的周期减少相同的量。作为最终结果，无论比较器中有任何偏移漂移，两个时钟周期的时间段将保持不变。

125. 发明授权

US09338694B2 Wireless communication system with SIPTO continuity 有权
标题翻译：具有SIPTO连续性的无线通信系统
公开(公告)号：US09338694B2
公开(公告)日：2016-05-10
申请号：US14306202
申请日：2014-06-16
申请人： Srinivas Reddy Lonka , Srinivasa Rao Addepalli , Naga Veera Venkata Raghava Rao Gunturu
发明人： Srinivas Reddy Lonka , Srinivasa Rao Addepalli , Naga Veera Venkata Raghava Rao Gunturu
IPC分类号： H04L12/26 , H04W28/12 , H04W36/22
CPC分类号： H04W28/12 , H04L45/22 , H04L45/38 , H04L45/64 , H04L47/2483 , H04W36/12 , H04W36/22 , H04W88/16
摘要： A communication system network element includes a Local Gateway co-located with a Home eNodeB. The Local Gateway has an open flow switch and a flow table, and provides service continuity of active SIPTO (selective IP traffic offload) sessions using open flow/software defined networking. An operator-controlled Open flow controller manages sessions at the Local Gateway. A flow modification feature is used to modify an existing flow in the flow table, which provides a means for interception and handover from a source Home eNodeB to a target Home eNodeB.
摘要翻译：通信系统网元包括与家庭eNodeB共同定位的本地网关。本地网关具有开放的流量开关和流程表，并使用开放式流量/软件定义的网络提供主动SIPTO（选择性IP流量卸载）会话的服务连续性。操作员控制的开放流量控制器管理本地网关的会话。流修改特征用于修改流表中的现有流，其提供用于从源家庭eNodeB到目标家庭eNodeB的截取和切换的手段。

126. 发明授权

US09337818B1 Buffer circuit for voltage controlled oscillator 有权
标题翻译：压控振荡器的缓冲电路
公开(公告)号：US09337818B1
公开(公告)日：2016-05-10
申请号：US14833122
申请日：2015-08-23
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Krishna Thakur , Deependra K. Jain , Devesh P. Singh , Anand Kumar Sinha , Avinash Chandra Tripathi
IPC分类号： H03L7/06 , H03K5/134 , H03K3/03 , H03K19/0185 , H03L7/08 , H03L7/099 , H03K5/00
CPC分类号： H03K5/134 , H03K3/0315 , H03K5/1508 , H03K19/018521 , H03K2005/00019 , H03L7/0805 , H03L7/0812 , H03L7/0995
摘要： A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.
摘要翻译：缓冲电路包括反相器和电平转换器。逆变器以第一电压电平接收第一振荡信号，并在第二电压电平下产生第一振荡信号的反相形式。电平移位器以与第一振荡信号相反的第三电压电平和反相的第一振荡信号接收第二振荡信号，并产生第四电压电平的缓冲器输出信号。

127. 发明授权

US09337140B1 Signal bond wire shield 有权
标题翻译：信号键线屏蔽
公开(公告)号：US09337140B1
公开(公告)日：2016-05-10
申请号：US14842816
申请日：2015-09-01
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Shailesh Kumar , Rishi Bhooshan , Meng Kong Lye , Sumit Varshney , Chetan Verma
IPC分类号： H01L23/495 , H01L23/522 , H01L23/00
CPC分类号： H01L23/5225 , H01L23/4952 , H01L23/49541 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/05014 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48253 , H01L2224/49171 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/30105 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor die having opposing first and second main surfaces, contact pads and a metal ring accessible from the first main surface, and signal leads surrounding and spaced from the die. Each of the signal leads has a first end near the die, a second end remote from the die, and a body extending between the first and second ends. A dummy lead frame is disposed between the signal leads first ends and the die, and connected to a fixed potential. First bond wires are coupled to respective ones of the signal leads and the contact pads. Second, shield bond wires, located adjacent to respective ones of the bond wires, are coupled to the dummy lead frame and the metal ring.
摘要翻译：半导体器件包括具有相对的第一和第二主表面，接触焊盘和可从第一主表面接近的金属环的半导体管芯，以及围绕并与管芯间隔开的信号引线。每个信号引线具有靠近管芯的第一端，远离管芯的第二端和在第一和第二端之间延伸的本体。虚拟引线框架设置在信号引线第一端和管芯之间，并连接到固定电位。第一接合线耦合到相应的信号引线和接触焊盘。第二，与相应的接合线相邻的屏蔽接合线被耦合到虚拟引线框架和金属环。

128. 发明授权

US09335805B2 Method and apparatus for managing power in a multi-core processor 有权
标题翻译：在多核处理器中管理电源的方法和装置
公开(公告)号：US09335805B2
公开(公告)日：2016-05-10
申请号：US13989280
申请日：2010-11-25
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/26 , G06F1/32 , G06F9/50
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

129. 发明授权

US09335170B2 Inertial sensor and method of levitation effect compensation 有权
标题翻译：惯性传感器和悬浮效应补偿方法
公开(公告)号：US09335170B2
公开(公告)日：2016-05-10
申请号：US13687299
申请日：2012-11-28
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Yizhen Lin , Jan Mehner , Michael Naumann
IPC分类号： G01C19/00 , G01C19/574
CPC分类号： G01C19/574
摘要： An inertial sensor (110) includes a drive system (118) configured to oscillate a drive mass (114) within a plane (24) that is substantially parallel to a surface (50) of a substrate (28). The drive system (118) includes first and second drive units (120, 122) having fixed fingers (134, 136) interleaved with movable fingers (130, 132) of the drive mass (114). At least one of the drive units (120) is located on each side (126, 128) of the drive mass (114). Likewise, at least one of the drive units (122) is located on each side (126, 128) of the drive mass (114). The drive units (122) are driven in phase opposition to the drive units (120) so that a levitation force (104) generated by the drive units (122) compensates for, or at least partially suppresses, a levitation force (100) generated by the drive units (120).
摘要翻译：惯性传感器（110）包括驱动系统（118），驱动系统（118）被配置为使基本平行于基底（28）的表面（50）的平面（24）内的驱动质量块（114）振荡。驱动系统（118）包括具有与驱动质量块（114）的活动指状物（130,132）交错的固定指状物（134,136）的第一和第二驱动单元（120,122）。驱动单元（120）中的至少一个位于驱动块（114）的每一侧（126,128）上。类似地，驱动单元（122）中的至少一个位于驱动块（114）的每一侧（126,128）上。驱动单元（122）与驱动单元（120）相反地驱动，使得由驱动单元（122）产生的悬浮力（104）补偿或至少部分地抑制产生的悬浮力（100）通过驱动单元（120）。

130. 发明申请

US20160126963A1 PHASE DETECTOR AND PHASE-LOCKED LOOP 有权
标题翻译：相位检测器和相位锁定环路
公开(公告)号：US20160126963A1
公开(公告)日：2016-05-05
申请号：US14895267
申请日：2013-06-06
申请人： Gennady Mihaylovich VYDOLOB
发明人： GENNADY MIHAYLOVICH VYDOLOB
IPC分类号： H03L7/089 , H03D13/00
CPC分类号： H03L7/0891 , H03D13/004 , H03L7/089 , H03L7/091 , H03L7/1077
摘要： A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1≦F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2≦F1 and the level “0” in response to F2>F1.
摘要翻译：提出了一种相位检测器，用于产生指示频率F1的第一双电平信号和频率为F2的第二双电平信号之间的相位差的相位差信号。相位检测器可以包括第一和第二检测器输入第一和第二触发器，NAND门以及第一和第二超相位检测单元。第一上相检测单元的输出可以连接到第二触发器的直接输入，并且可以被布置为响应于F1> N1而输出电平“1”;响应于F1> F2而输出电平“0” 。第二过相检测单元的输出可以连接到第一触发器的直接输入，并且可以被布置为响应于F2> n1而输出电平“1”; F1和响应于F2> F1的电平“0” 。

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