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1. 发明授权

US10402198B2 Signal processing device and method of performing a pack-insert operation 有权
公开(公告)号：US10402198B2
公开(公告)日：2019-09-03
申请号：US14897787
申请日：2013-06-18
申请人： Avi Gal , Fabrice Aidan , Noam Eshel-Goldman , Roy Glasner , Dmitry Lachover , Itay Peled
发明人： Avi Gal , Fabrice Aidan , Noam Eshel-Goldman , Roy Glasner , Dmitry Lachover , Itay Peled
IPC分类号： G06F9/30 , H03M13/27 , H03M13/00
摘要： A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

2. 发明申请

US20130275725A1 INTEGRATED CIRCUIT DEVICE AND METHOD FOR PERFORMING CONDITIONAL NEGATION OF DATA 审中-公开
标题翻译：集成电路设备和数据处理条件的方法
公开(公告)号：US20130275725A1
公开(公告)日：2013-10-17
申请号：US13995190
申请日：2011-01-03
申请人： Ilia Moskovich , Fabrice Aidan , Avi Gal , Dmitry Lachover
发明人： Ilia Moskovich , Fabrice Aidan , Avi Gal , Dmitry Lachover
IPC分类号： G06F9/30
CPC分类号： G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/30072
摘要： An integrated circuit device comprising at least one digital signal processor (DSP) module, the at least one DSP module comprising a first data register and at least one further data register and at least one data execution unit (DEU) module arranged to execute operations on target data stored within the first data register and the at least one further data register. The at least one DEU module is arranged, upon receipt of a conditional negation instruction, to retrieve at least one conditional bit value from the first data register, and conditionally perform negation of target data within the at least one further data register according to the at least one retrieved conditional bit value.
摘要翻译：一种集成电路装置，包括至少一个数字信号处理器（DSP）模块，所述至少一个DSP模块包括第一数据寄存器和至少一个另外的数据寄存器，以及至少一个数据执行单元（DEU）模块，存储在第一数据寄存器和至少一个另外的数据寄存器中的目标数据。在接收到条件否定指令时，至少一个DEU模块被布置成从第一数据寄存器中检索至少一个条件位值，并且有条件地执行根据at的至少一个另外的数据寄存器中的目标数据的否定至少一个检索到的条件位值。

3. 发明授权

US06480874B1 Power saving method for performing additions and subtractions and a device thereof 失效
标题翻译：用于执行加法和减法的省电方法及其装置
公开(公告)号：US06480874B1
公开(公告)日：2002-11-12
申请号：US09436890
申请日：1999-11-09
申请人： Fabrice Aidan , Yoram Salant , Mark Elnekave , Leonid Tsukerman
发明人： Fabrice Aidan , Yoram Salant , Mark Elnekave , Leonid Tsukerman
IPC分类号： G06F750
CPC分类号： G06F7/5055
摘要： A power saving device and method for either adding or subtracting a constant from an operand, by checking a logic value of a portion of the operand and deciding whether to activate a multi-bit adder or to perform the subtraction or addition by inverting a portion of the operand. The power saving device and method is especially efficient when the constant K equals 2n. Then, the n'th bit of the operand is checked and if the addition or subtraction operation can be performed by inverting the n'th bit of the operand, a result is generated by that inversion, while a multi-bit adder is disabled.
摘要翻译：一种省电装置和方法，用于通过检查所述操作数的一部分的逻辑值并且决定是激活多位加法器还是通过反转一部分的一部分来执行所述减法或加法来从操作数增加或减去常数操作数。当常数K等于2n时，省电装置和方法特别有效。然后，检查操作数的第n位，并且如果可以通过反转操作数的第n位来执行加法或减法操作，则通过该反转产生结果，而禁止多位加法器。

4. 发明申请

US20160132332A1 SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION 审中-公开
标题翻译：信号处理装置和执行位扩展操作的方法
公开(公告)号：US20160132332A1
公开(公告)日：2016-05-12
申请号：US14898353
申请日：2013-06-18
申请人： Roy GLASNER , Fabrice AIDAN , Aviram AMIR , Noam ESHEL-GOLDMAN , Avi GAL , Ilia MOSKOVICH
发明人： ROY GLASNER , FABRICE AIDAN , AMIR AVIRAM , NOAM ESHEL-GOLDMAN , AVI GAL , ILIA MOSKOVICH
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30098
摘要： A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.
摘要翻译：一种信号处理装置，包括至少一个控制单元，其被配置为接收至少一个位扩展指令，对所接收的至少一个位扩展指令进行解码，以及根据接收的至少一个位扩展来输出至少一个控制信号指令。所述信号处理设备还包括至少一个执行单元组件，被布置为接收包括至少一个要扩展的数据位的至少一个源寄存器值，从位于偏移位置的至少一个源寄存器值提取至少一个数据位根据至少一个控制信号，将至少一个提取的数据位扩展为至少一个多位数据类型，并将至少一个多位数据类型输出到至少一个目标寄存器。

5. 发明授权

US06757701B2 Apparatus and method for implementing a linearly approximated log map algorithm 有权
标题翻译：用于实现线性近似的对数映射算法的装置和方法
公开(公告)号：US06757701B2
公开(公告)日：2004-06-29
申请号：US09923007
申请日：2001-08-03
申请人： Noam Sivan , Fabrice Aidan , Gregory Leshin
发明人： Noam Sivan , Fabrice Aidan , Gregory Leshin
IPC分类号： G06F738
CPC分类号： H03M13/3911
摘要： A method and apparatus for implementing a linearly approximated Log MAP algorithm, the implementation involves calculating MAX*(a(n),b(n)) function, the method having the steps of: (A) Receiving a(n), b(n) and a value DE; (B) calculating (a(n)+b(n)+DE/2 and generating at least one intermediate result, the at least one intermediate result reflecting at least one relationship between at least two elements out of a(n), b(n) and DE; and (C) providing an MAX*(a(n),b(n)) result selected from a group comprising of a(n), b(n) or (a(n)+b(n)+DE)/2, the selection dependent upon the at least one intermediate result.
摘要翻译：一种用于实现线性近似Log MAP算法的方法和装置，该实现涉及计算MAX *（a（n），b（n））函数，该方法具有以下步骤：（A）接收a（n），b n）和值DE; （B）计算（a（n）+ b（n）+ DE / 2并生成至少一个中间结果，所述至少一个中间结果反映出a（n），b （n）和DE;以及（C）提供从包括a（n），b（n）或（a（n）+ b（n））的组中选择的MAX *（a（n），b n）+ DE）/ 2，选择取决于至少一个中间结果。

6. 发明申请

US20160188331A1 SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A PACK-INSERT OPERATION 审中-公开
标题翻译：信号处理装置和执行包插入操作的方法
公开(公告)号：US20160188331A1
公开(公告)日：2016-06-30
申请号：US14897787
申请日：2013-06-18
申请人： Avi GAL , Fabrice AIDAN , Noam ESHEL-GOLDMAN , Roy GLASNER , Dmitry LACHOVER , Itay PELED
发明人： AVI GAL , FABRICE AIDAN , NOAM ESHEL-GOLDMAN , ROY GLASNER , DMITRY LACHOVER , ITAY PELED
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30098 , H03M13/2757 , H03M13/6525
摘要： A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.
摘要翻译：一种信号处理设备，包括至少一个控制单元，该控制单元被布置为接收至少一个包装插入指令，对接收到的至少一个包装插入指令进行解码，并且根据接收到的包装插入物输出至少一个包装插入控制信号指令。所述信号处理设备还包括至少一个包插入组件，其被布置为接收要插入到要输出到至少一个目的地寄存器的数据块序列中的至少第一数据块，接收多个另外的数据块为打包在要输出到至少一个目的地寄存器的数据块序列内，至少部分地基于至少一个包插入件将至少第一数据块和多个另外的数据块排列成数据块序列控制信号，并输出数据块序列。

7. 发明授权

US06654871B1 Device and a method for performing stack operations in a processing system 有权
标题翻译：用于在处理系统中执行堆栈操作的装置和方法
公开(公告)号：US06654871B1
公开(公告)日：2003-11-25
申请号：US09436891
申请日：1999-11-09
申请人： Fabrice Aidan , Yoram Salant , Mark Elnekave , Leonid Tsukerman
发明人： Fabrice Aidan , Yoram Salant , Mark Elnekave , Leonid Tsukerman
IPC分类号： G06F942
CPC分类号： G06F9/30163 , G06F7/78 , G06F9/4484
摘要： A method and a device for performing stack operations within a processing system. A first and second stack pointers point to a top of a stack and to a memory location following the top of the stack. A first stack pointer is used during pop operations and a second stack pointer is used during push operations. When a stack pointer is selected, it replaces the other stack pointer. The selected memory pointer is provided to a memory module in which a stack is implemented, and is also updated. When a pop operation is executed the updated stack pointer points to a memory location preceding a memory location pointed by the selected stack pointer and when a push operation is executed the updated stack pointer points to a memory address following that address.
摘要翻译：一种用于在处理系统内执行堆栈操作的方法和装置。第一个和第二个堆栈指针指向堆栈的顶部和堆栈顶部之后的存储器位置。弹出操作期间使用第一个堆栈指针，并在推送操作期间使用第二个堆栈指针。当选择堆栈指针时，它将替换另一个堆栈指针。所选择的存储器指针被提供给其中实现堆栈的存储器模块，并且还被更新。当执行弹出操作时，更新的堆栈指针指向由所选择的堆栈指针指向的存储器位置之前的存储器位置，并且当执行推送操作时，更新的堆栈指针指向该地址之后的存储器地址。

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