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111. 发明授权

US5379256A Electrically erasable programmable read-only memory with write/verify controller 失效
标题翻译：具有写/验证控制器的电可擦除可编程只读存储器
公开(公告)号：US5379256A
公开(公告)日：1995-01-03
申请号：US223307
申请日：1994-04-05
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
IPC分类号： G11C7/06 , G11C16/10 , G11C16/26 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/26 , G11C16/3454 , G11C7/067
摘要： A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.
摘要翻译：多个电可擦除可编程只读存储器或EEPROM与控制器LSI相关联。每个EEPROM包括以行和列排列的浮栅隧穿存储单元晶体管阵列。当选择提供单页数据的存储单元晶体管的子阵列进行编程时，控制器LSI通过检查所选存储单元晶体管的阈值来验证所选择的存储单元晶体管的编程之后，如下进行写入/校验操作变化的值，并且当任何潜在的不足的单元晶体管保持在其中之间时，重复使用预定时间段的预定写入电压的重写操作，使得所得到的写入状态可能更接近可满足的参考状态。通过将写入电压施加到不足的单元晶体管预定时间段来执行每个重写/验证操作。

112. 发明授权

US5357462A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US5357462A
公开(公告)日：1994-10-18
申请号：US948002
申请日：1992-09-21
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据根据实际写入状态对每个位线进行电路验证。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

113. 发明授权

US5278794A NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit 失效
标题翻译：具有冗余电路的NAND单元型电可擦除可编程只读存储器
公开(公告)号：US5278794A
公开(公告)日：1994-01-11
申请号：US960882
申请日：1992-10-14
申请人： Yoshiyuki Tanaka , Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka
发明人： Yoshiyuki Tanaka , Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/04 , G11C11/40 , G11C5/02
CPC分类号： G11C29/789 , G11C16/0483 , G11C29/808 , G11C29/82
摘要： A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.
摘要翻译： NAND单元型电可擦除和可编程只读存储器包括与半导体基板上的并行位线相关联的存储单元的行和列阵列。每个存储单元基本上由具有浮置栅极和绝缘控制栅极的浮栅场效应晶体管组成。存储单元阵列被分成多个单元块，每个单元块包括每个包括预定数量的串联存储单元晶体管的NAND单元部分。提供冗余单元部分，其包括包含至少一个备用单元块的冗余存储单元的阵列。行冗余电路连接到行解码器，并响应于地址缓冲器。冗余电路用备用单元块替代含有缺陷存储单元或单元的缺陷块。

114. 发明授权

US06477087B2 Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US06477087B2
公开(公告)日：2002-11-05
申请号：US09893544
申请日：2001-06-29
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C1612
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据根据实际写入状态对每个位线进行电路验证。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

115. 发明授权

US06285591B1 Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：用自动写入验证控制器对电可擦除和可编程的非易失性半导体存储器进行编程的方法
公开(公告)号：US06285591B1
公开(公告)日：2001-09-04
申请号：US09472152
申请日：1999-12-27
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C1610
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation if the write data. A program controller is provided for writing the data into a selected memory cell in the designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且如果写入数据，则选择性地执行检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的选定存储单元，并用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并且写入数据被锁存在感测锁存电路中，并且用于自动更新存储在感测/锁存电路中的重写数据相对于根据实际写入状态被验证的每个位线。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

116. 发明授权

US6026025A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US6026025A
公开(公告)日：2000-02-15
申请号：US96466
申请日：1998-06-12
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据根据实际写入状态对每个位线进行电路验证。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

117. 发明授权

US5768190A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US5768190A
公开(公告)日：1998-06-16
申请号：US749935
申请日：1996-11-14
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM having an array of memory cells connected to bit lines. Each cell includes one transistor with floating and control gate electrodes. Electrons are tunneled to or from the floating gate to write data. A sense/latch circuit is connected to the bit lines for selectively performing sense and latch operations of the write data. A program controller is provided for writing and verifying the data into a selected memory cell. Data is rewritten if a resultant threshold voltage in the selected memory cell of the written data is insufficient. A rewrite-data setting section is provided for performing a logic operation with respect to data read from the selected cell and write data being latched into the sense/latch circuit, and for automatically updating a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the memory being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.
摘要翻译：具有连接到位线的存储器单元阵列的NAND单元型EEPROM。每个单元包括具有浮置和控制栅电极的一个晶体管。电子通过隧道传输到浮动栅极或从浮动栅极写入数据。感测/锁存电路连接到位线，用于选择性地执行写入数据的检测和锁存操作。提供了一种程序控制器，用于将数据写入和验证到选定的存储单元中。如果写入数据的选定存储单元中的合成阈值电压不足，则重写数据。提供重写数据设置部分，用于执行关于从所选择的单元读取的数据的逻辑操作和被锁存到感测/锁存电路中的写入数据，并且用于自动更新存储在感测/锁存电路中的重写数据，根据正在验证的存储器对每个位线进行操作。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

118. 发明授权

US5627782A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US5627782A
公开(公告)日：1997-05-06
申请号：US473739
申请日：1995-06-07
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据根据实际写入状态对每个位线进行电路验证。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

119. 发明授权

US5740112A Sense amplifier for use in an EEPROM 失效
标题翻译：用于EEPROM的感应放大器
公开(公告)号：US5740112A
公开(公告)日：1998-04-14
申请号：US583533
申请日：1996-01-04
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
IPC分类号： G11C7/06 , G11C16/10 , G11C16/26 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/26 , G11C16/3454 , G11C7/067
摘要： A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.
摘要翻译：用于电可擦除和可编程只读存储器（EEPROM）中的信号检测用读出放大器。读出放大器包括：第一时钟信号同步反相器，包括第一反相器和用于在第一反相器的激活和去激活状态之间切换的第一开关，第一时钟信号同步反相器具有连接到对应的一个位线的第一输入和第一个输出。第二时钟信号同步反相器与第一时钟信号同步反相器并联布置，并且包括第二反相器和用于在第二反相器的激活和去激活状态之间切换的第二开关，第二时钟信号同步反相器具有输入连接到第一时钟信号同步反相器的输出端，以及连接到第一时钟信号同步反相器的输入端的输出端。第一和第二时钟信号同步反相器中的开关被延迟激活，使得对应位线上的电位被可靠地感测并锁存在第一时钟信号同步反相器的输出端。

120. 发明授权

US5566105A Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
公开(公告)号：US5566105A
公开(公告)日：1996-10-15
申请号：US277514
申请日：1994-07-19
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

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