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1. 发明授权

US06285591B1 Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller 失效
标题翻译：用自动写入验证控制器对电可擦除和可编程的非易失性半导体存储器进行编程的方法
公开(公告)号：US06285591B1
公开(公告)日：2001-09-04
申请号：US09472152
申请日：1999-12-27
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C1610
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation if the write data. A program controller is provided for writing the data into a selected memory cell in the designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.
摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。感测/锁存电路连接到位线，并且如果写入数据，则选择性地执行检测操作和锁存操作。提供了一种程序控制器，用于将数据写入指定区域中的选定存储单元，并用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。如果不足，则重写数据。提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并且写入数据被锁存在感测锁存电路中，并且用于自动更新存储在感测/锁存电路中的重写数据相对于根据实际写入状态被验证的每个位线。感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

2. 发明授权

US06574147B2 Electrically erasable and programmable nonvolatile semiconductor memory with automatic write-verify controller 失效
标题翻译：具有自动写入验证控制器的电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US06574147B2
公开(公告)日：2003-06-03
申请号：US10101213
申请日：2002-03-20
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Hiroshi Nakamura , Hideko Odaira
IPC分类号： G11C1610
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3454
摘要： A method for controlling programming of an electrically erasable and programmable nonvolatile memory having a plurality of memory cells, row and column decoders, an address buffer, and a bit line controller including a sense/latch circuit and a data I/O buffer, including supplying address signals to the address buffer to define at least one selected memory cell in the plurality of memory cells; supplying to the bit line controller programming data which corresponds to write data to be written in the selected memory cell; latching the programming data in the sense/latch circuit; writing the write data into the selected memory cell; reading the written data of the selected memory cell and verifying whether or not the data is successfully written; performing a logic operation with respect to the read data and the programming data latched in the sense/latch circuit to determine if the written memory cell is insufficiently written or successfully written; and if an insufficiently written memory cell is found, maintaining the programming data and rewriting the write data into the insufficiently written memory cell.
摘要翻译：一种用于控制具有多个存储器单元，行和列解码器，地址缓冲器和包括感测/锁存电路和数据I / O缓冲器的位线控制器的电可擦除和可编程非易失性存储器的编程的方法，包括：将地址信号发送到地址缓冲器以限定多个存储器单元中的至少一个选择的存储单元; 向位线控制器提供对应于要写入所选存储单元的写入数据的编程数据; 将编程数据锁存在感测/锁存电路中; 将写数据写入所选存储单元; 读取所选存储单元的写入数据并验证数据是否被成功写入; 对读取的数据和锁存在感测/锁存电路中的编程数据执行逻辑运算，以确定写入的存储器单元是否写入不足或成功写入; 并且如果找到写入不足的存储单元，则保持编程数据并将写入数据重写为写入不足的存储单元。

3. 发明授权

US06795344B2 Floating gate memory architecture with program voltage stable circuit 有权
标题翻译：具有编程电压稳定电路的浮动存储架构
公开(公告)号：US06795344B2
公开(公告)日：2004-09-21
申请号：US10316851
申请日：2002-12-12
申请人： Yeh Jun Lin
发明人： Yeh Jun Lin
IPC分类号： G11C1610
CPC分类号： G11C16/30
摘要： A floating gate memory architecture having current regulator is disclosed. A floating gate memory block have at least a programming voltage node for being programmed a plurality of bits according to the control of a plurality of bit lines. A high voltage source provides a regulated voltage when the plurality of bits are programmed in. A high voltage decoder locates between the floating gate memory block and the high voltage source for connecting the voltage to the programming voltage node according to the programming data of the floating gate memory block. A current regulator connects to the programming voltage node for keeping the programming voltage node in a constant voltage, and making a constant current flowing into said floating gate memory block according to said plurality of bits.
摘要翻译：公开了一种具有电流调节器的浮动存储架构。浮动栅极存储块至少具有编程电压节点，用于根据多个位线的控制来编程多个位。当多个位被编程时，高电压源提供调节电压。高电压解码器位于浮动栅极存储器块和高电压源之间，用于根据浮动的编程数据将电压连接到编程电压节点门内存块。电流调节器连接到编程电压节点，用于将编程电压节点保持在恒定电压，并根据所述多个位使恒定电流流入所述浮动栅极存储器块。

4. 发明授权

US06570785B1 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06570785B1
公开(公告)日：2003-05-27
申请号：US09703083
申请日：2000-10-31
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
IPC分类号： G11C1610
CPC分类号： G11C16/12
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

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