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1. 发明授权

US5740112A Sense amplifier for use in an EEPROM 失效
标题翻译：用于EEPROM的感应放大器
公开(公告)号：US5740112A
公开(公告)日：1998-04-14
申请号：US583533
申请日：1996-01-04
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
IPC分类号： G11C7/06 , G11C16/10 , G11C16/26 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/26 , G11C16/3454 , G11C7/067
摘要： A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.
摘要翻译：用于电可擦除和可编程只读存储器（EEPROM）中的信号检测用读出放大器。读出放大器包括：第一时钟信号同步反相器，包括第一反相器和用于在第一反相器的激活和去激活状态之间切换的第一开关，第一时钟信号同步反相器具有连接到对应的一个位线的第一输入和第一个输出。第二时钟信号同步反相器与第一时钟信号同步反相器并联布置，并且包括第二反相器和用于在第二反相器的激活和去激活状态之间切换的第二开关，第二时钟信号同步反相器具有输入连接到第一时钟信号同步反相器的输出端，以及连接到第一时钟信号同步反相器的输入端的输出端。第一和第二时钟信号同步反相器中的开关被延迟激活，使得对应位线上的电位被可靠地感测并锁存在第一时钟信号同步反相器的输出端。

2. 发明授权

US4725915A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4725915A
公开(公告)日：1988-02-16
申请号：US717695
申请日：1985-03-29
申请人： Hiroshi Jwahashi , Masamichi Asano , Hiroshi Harada , Shinichi Tanaka , Hideki Sumihara
发明人： Hiroshi Jwahashi , Masamichi Asano , Hiroshi Harada , Shinichi Tanaka , Hideki Sumihara
IPC分类号： G11C16/10 , H01L27/02 , H01L27/088 , H01L29/78 , H03K3/353
CPC分类号： H01L27/0251 , G11C16/10 , H01L27/088
摘要： A semiconductor integrated circuit includes a MOS transistor, and a transistor circuit in which one end of a current path is connected to a drain of this MOS transistor and which has an avalanche breakdown voltage lower than a breakdown voltage of the MOS transistor.
摘要翻译：半导体集成电路包括MOS晶体管和晶体管电路，其中电流路径的一端连接到该MOS晶体管的漏极，并且具有低于MOS晶体管的击穿电压的雪崩击穿电压。

3. 发明授权

US5379256A Electrically erasable programmable read-only memory with write/verify controller 失效
标题翻译：具有写/验证控制器的电可擦除可编程只读存储器
公开(公告)号：US5379256A
公开(公告)日：1995-01-03
申请号：US223307
申请日：1994-04-05
申请人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
发明人： Tomoharu Tanaka , Yoshiyuki Tanaka , Kazunori Ohuchi , Masaki Momodomi , Yoshihisa Iwata , Koji Sakui , Shinji Saito , Hideki Sumihara
IPC分类号： G11C7/06 , G11C16/10 , G11C16/26 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/26 , G11C16/3454 , G11C7/067
摘要： A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.
摘要翻译：多个电可擦除可编程只读存储器或EEPROM与控制器LSI相关联。每个EEPROM包括以行和列排列的浮栅隧穿存储单元晶体管阵列。当选择提供单页数据的存储单元晶体管的子阵列进行编程时，控制器LSI通过检查所选存储单元晶体管的阈值来验证所选择的存储单元晶体管的编程之后，如下进行写入/校验操作变化的值，并且当任何潜在的不足的单元晶体管保持在其中之间时，重复使用预定时间段的预定写入电压的重写操作，使得所得到的写入状态可能更接近可满足的参考状态。通过将写入电压施加到不足的单元晶体管预定时间段来执行每个重写/验证操作。

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