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111. 发明申请

US20060023547A1 Semiconductor memory 失效
公开(公告)号：US20060023547A1
公开(公告)日：2006-02-02
申请号：US11215045
申请日：2005-08-31
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

112. 发明申请

US20060015788A1 Semiconductor device 有权
公开(公告)号：US20060015788A1
公开(公告)日：2006-01-19
申请号：US11206170
申请日：2005-08-18
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/48 , G11C29/36
摘要： A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.

113. 发明授权

US06961881B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06961881B2
公开(公告)日：2005-11-01
申请号：US10122181
申请日：2002-04-16
申请人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
发明人： Masafumi Yamazaki , Takaaki Suzuki , Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo , Ayako Sato , Takayuki Yoneda , Noriko Kawamura
IPC分类号： G11C29/00 , G11C29/36 , G11C29/48
CPC分类号： G11C29/48 , G11C29/36
摘要： A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.
摘要翻译：由逻辑芯片访问的逻辑芯片和存储器芯片安装在单个封装中。逻辑芯片的模式发生器在第一测试模式下操作以产生用于存储器芯片的内部测试模式。模式选择器在第一测试模式期间选择从模式发生器输出的内部测试模式，在第二测试模式期间，选择通过测试终端提供的外部测试模式，并将所选择的测试模式输出到存储芯片。通过使用模式选择信号，在第二测试模式中使用在逻辑芯片内产生的第一测试模式中的内部测试模式或外部测试模式来测试安装在封装中的存储芯片，从外部。

114. 发明申请

US20050164918A1 Segment of glycosylation-deficient HGFalpha-chain 有权
标题翻译：糖基化缺陷型HGFalpha链的区段
公开(公告)号：US20050164918A1
公开(公告)日：2005-07-28
申请号：US10926088
申请日：2004-08-26
申请人： Toshikazu Nakamura , Kunio Matsumoto , Kazuhiro Fukuta
发明人： Toshikazu Nakamura , Kunio Matsumoto , Kazuhiro Fukuta
IPC分类号： A61K38/00 , C07K14/475 , A61K38/18
CPC分类号： C07K14/4753
摘要： The present invention provides a segment of glycosylation-deficient HGF having mutation(s) introduced into an amino acid sequence so as to prevent glycosylation at at least one glycosylation site of a hepatocyte growth factor (HGF), and a method of producing the same. The segment of glycosylation-deficient HGF of the present invention has the same activity as that of a segment of glycosylated HGF, therefore, it is useful as an alternate for a segment of glycosylated HGF.
摘要翻译：本发明提供了具有引入氨基酸序列的突变以防止肝细胞生长因子（HGF）的至少一个糖基化位点处的糖基化的糖基化缺陷型HGF的片段及其制备方法。本发明的糖基化缺陷型HGF片段具有与糖基化HGF片段相同的活性，因此，作为糖基化HGF片段的替代物是有用的。

115. 发明授权

US06819610B2 DRAM operating like SRAM 失效
标题翻译： DRAM像SRAM一样运行
公开(公告)号：US06819610B2
公开(公告)日：2004-11-16
申请号：US10267873
申请日：2002-10-10
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto , Ayako Sato , Masato Matsumiya
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto , Ayako Sato , Masato Matsumiya
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4094
摘要： A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.
摘要翻译：半导体存储器件包括经由晶体管连接到存储单元的第一位线，传输门，经由传输门连接到第一位线的第二位线，连接到第二位线的读出放大器，第一预充电用于对第一位线进行预充电的电路，用于对第二位线进行预充电的第二预充电电路，在关闭传输门之后由第一预充电电路对第一位线进行预充电的控制电路，随后通过第二位线预先充电第二位线第二预充电电路。

116. 发明授权

US06699837B2 Treatment of neurons with HGF 失效
标题翻译：用HGF处理神经元
公开(公告)号：US06699837B2
公开(公告)日：2004-03-02
申请号：US08605221
申请日：1996-03-15
申请人： Toshikazu Nakamura
发明人： Toshikazu Nakamura
IPC分类号： A61K3818
CPC分类号： C07K14/4753 , A61K38/1833
摘要： The invention relates to a therapeutic agent for disorder in brain and nerve containing HGF (hepatocyte growth factor) as an active ingredient, and a method for treatment of disorder in brain and nerve comprising administration of HGF. The active ingredient HGF possesses an action to prolong survival of brain and nerve cells, and the injured brain or nerves may be regenerated and restored. Therefore, the therapeutic agent and method for treatment of the invention are useful for prevention and treatment of various disorder in brain and nerve (for example, dementia, senile dementia of Alzheimer type, cerebral stroke, and cerebral infarction).
摘要翻译：本发明涉及含有HGF（肝细胞生长因子）作为活性成分的脑和神经疾病治疗剂，以及治疗脑和神经紊乱的方法，包括施用HGF。活性成分HGF具有延长脑和神经细胞存活的作用，可以再生和恢复损伤的脑或神经。因此，用于治疗本发明的治疗剂和方法可用于预防和治疗脑和神经中的各种障碍（例如，痴呆，老年痴呆型老年痴呆，脑卒中和脑梗死）。

117. 发明授权

US06548903B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06548903B2
公开(公告)日：2003-04-15
申请号：US10066630
申请日：2002-02-06
申请人： Toshikazu Nakamura , Toshiya Miyo
发明人： Toshikazu Nakamura , Toshiya Miyo
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L27/0207 , H01L27/10882 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.
摘要翻译：在第一和第二区域中，通过使用具有各自的不同布线层的数据线来传送未并发传送的数据。数据线的垂直位置在第一和第二区域之间相反。在切换区域中，在第一和第二区域之间交换数据线。与两个数据线相关联的寄生电容实际上彼此相等，使得沿着数据线传送的信号的延迟时间彼此相等。这可以防止由寄生电容差引起的电路故障。在其中存储单元阵列和读出放大器阵列交替布线的半导体集成电路中，在存储单元阵列和感测放大器阵列上的开关区域之间形成第一和第二区域使得更容易将数据线的垂直位置开关区域。

118. 发明授权

US06252269B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06252269B1
公开(公告)日：2001-06-26
申请号：US09422860
申请日：1999-10-25
申请人： Masatomo Hasegawa , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii
发明人： Masatomo Hasegawa , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii
IPC分类号： H01L27108
CPC分类号： H01L21/8249 , H01L27/0214 , H01L27/0623 , H01L27/105 , H01L27/10897
摘要： According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.
摘要翻译：根据本发明的一个方面的半导体存储器，在形成在P型半导体衬底的表面的P型第一阱区域中形成存储单元晶体管，并且将反向偏置电压施加到 P型第一阱区和P型衬底。此外，通过注入高能N型杂质形成N型逆行区域，从而通过采用N型逆行区域形成较深的N型第二阱区域。此外，在N型第二阱区中形成P型第三阱区，并且还在其中形成P型发射极区。因此，P型发射极区域，N型第二阱区域和P型第三阱区域一起构成横向PNP晶体管。此外，为作为集电极区域的P型第三阱区域保持接地电压。

119. 发明授权

US06229363B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06229363B1
公开(公告)日：2001-05-08
申请号：US09224354
申请日：1999-01-04
申请人： Satoshi Eto , Masato Matsumiya , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Satoshi Eto , Masato Matsumiya , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03L708
CPC分类号： G11C7/1057 , G06F1/10 , G11C7/1051 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.
摘要翻译：具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时，第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

120. 发明授权

US06134771A Method of encasing leads of an electronic part 失效
标题翻译：封装电子部件引线的方法
公开(公告)号：US06134771A
公开(公告)日：2000-10-24
申请号：US775303
申请日：1996-12-31
申请人： Toshikazu Nakamura , Takashi Shikama
发明人： Toshikazu Nakamura , Takashi Shikama
IPC分类号： H01C1/14 , H01C7/02 , H01C7/04 , H01R43/16
CPC分类号： H01C1/1406 , H01C1/1413 , Y10T29/49085 , Y10T29/49204
摘要： An electronic part in which insulating tape is adhered to lead terminals which extend from an electronic part unit so that a pitch between the terminals can remain stable and constant. The insulating tape is adhered to portions of the lead terminals in a vicinity of the unit from both sides such that the tape is placed with the terminals therebetween.
摘要翻译：一种电子部件，其中绝缘带粘附到从电子部件单元延伸的引线端子，使得端子之间的间距能够保持稳定和恒定。绝缘带从两侧粘附到单元附近的引线端子的部分，使得带被放置在其间的端子。

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