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101. 发明授权

US07176093B2 Semiconductor processing methods of forming integrated circuitry 有权
标题翻译：形成集成电路的半导体处理方法
公开(公告)号：US07176093B2
公开(公告)日：2007-02-13
申请号：US10376106
申请日：2003-02-26
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/823425 , H01L27/1052 , H01L27/10894
摘要： Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.
摘要翻译：描述形成集成电路的半导体处理方法。在一个实施例中，在衬底上形成存储器电路和外围电路。外围电路包括第一和第二类型的MOS晶体管。在比第一类型的所有外围MOS晶体管少的情况下，将第二类型的晕轮植入物导入第一类型的MOS晶体管。在另一个实施例中，多个n型晶体管器件形成在衬底上并且包括存储器阵列电路和外围电路。至少一些单独的外围电路n型晶体管器件被部分屏蔽，并且对部分屏蔽的外围电路n型晶体管器件的未屏蔽部分进行晕圈注入。在另一个实施例中，源极和漏极区域中的仅一个区域的至少一部分被掩蔽，并且源极和漏极区域中的另一个的至少一部分被暴露用于至少一些外围电路n型晶体管器件。相对于源极和漏极区域的暴露部分进行晕轮植入。在另一个实施例中，使用公共屏蔽步骤，并且在衬底上形成的器件进行晕轮注入，该器件包括存储器电路和外围电路，其足以赋予器件中的至少三个器件三个不同的相应阈值电压。

102. 发明授权

US07170124B2 Trench buried bit line memory devices and methods thereof 有权
公开(公告)号：US07170124B2
公开(公告)日：2007-01-30
申请号：US10968429
申请日：2004-10-19
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

103. 发明授权

US07157775B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07157775B2
公开(公告)日：2007-01-02
申请号：US10367520
申请日：2003-02-13
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L29/76
CPC分类号： H01L27/10894 , H01L21/28044 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L27/10873 , H01L27/10888 , H01L27/10891 , H01L29/1041 , H01L29/4916 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/78 , Y10S438/919 , Y10S438/975
摘要： The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying subregions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.
摘要翻译：本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。一对晶体管结构位于沟道区上方并由隔离区隔开。晶体管具有比底层子区域宽的栅极。本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。本发明还包括形成半导体结构的方法。

104. 发明授权

US07153778B2 Methods of forming openings, and methods of forming container capacitors 有权
公开(公告)号：US07153778B2
公开(公告)日：2006-12-26
申请号：US10783843
申请日：2004-02-20
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

105. 发明授权

US07057257B2 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry 有权
公开(公告)号：US07057257B2
公开(公告)日：2006-06-06
申请号：US10071453
申请日：2002-02-08
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L27/108
CPC分类号： H01L21/823481 , H01L27/10894 , H01L27/10897
摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

106. 发明授权

US07020039B2 Isolation device over field in a memory device 失效
标题翻译：隔离设备在存储设备中的字段
公开(公告)号：US07020039B2
公开(公告)日：2006-03-28
申请号：US10998483
申请日：2004-11-29
申请人： Luan C. Tran , Stephen R. Porter , Scot M. Graham , Steven E. Howell
发明人： Luan C. Tran , Stephen R. Porter , Scot M. Graham , Steven E. Howell
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译：存储器件包括位于存储器单元之间的隔离器件。多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

107. 发明授权

US06914287B2 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry 有权
公开(公告)号：US06914287B2
公开(公告)日：2005-07-05
申请号：US10931368
申请日：2004-08-31
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/108 , H01L21/00
CPC分类号： H01L21/823481 , H01L27/10894 , H01L27/10897
摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.

108. 发明授权

US06894915B2 Method to prevent bit line capacitive coupling 有权
标题翻译：防止位线电容耦合的方法
公开(公告)号：US06894915B2
公开(公告)日：2005-05-17
申请号：US10295225
申请日：2002-11-15
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： G11C5/06 , G11C7/18 , G11C11/4097 , H01L21/8242
CPC分类号： H01L27/10885 , G11C5/063 , G11C7/18 , G11C11/4097 , H01L27/10888 , H01L27/10891
摘要： Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer, and epitaxial layer include voltage contacts that allow for the wells to be biased to a de voltage level. The memory cell includes a transistor which is formed on the epitaxial layer, the transistor including a source and drain region separated by a channel region. The trench bit line is formed within the buried layer, and is coupled to the drain region of the transistor by a bit contact.
摘要翻译：提供了利用在掩埋层内形成的沟槽位线的存储单元的结构，系统和方法。存储单元形成在三阱结构中，其包括衬底，掩埋层和外延层。衬底，掩埋层和外延层包括允许阱被偏置到电压电平的电压触点。存储单元包括形成在外延层上的晶体管，晶体管包括由沟道区分开的源极和漏极区域。沟槽位线形成在掩埋层内，并通过位接触耦合到晶体管的漏极区域。

109. 发明授权

US06759288B2 Double LDD devices for improved DRAM refresh 失效
标题翻译：双LDD器件可改善DRAM刷新
公开(公告)号：US06759288B2
公开(公告)日：2004-07-06
申请号：US10208830
申请日：2002-08-01
申请人： Luan C. Tran , Mark McQueen , Robert Kerr
发明人： Luan C. Tran , Mark McQueen , Robert Kerr
IPC分类号： H01L21337
CPC分类号： H01L27/10894 , H01L27/10897 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.
摘要翻译：提供了具有改进的DRAM刷新特性的集成电路器件，以及制造该器件的新颖方法。半导体基板在阵列部分和周边部分中的表面上设置有栅极结构。单个轻掺杂区域通过在衬底中的离子注入形成在沟道区附近。具有第一宽度的电介质间隔物形成在与覆盖单个轻掺杂区域的至少一部分的栅极结构相邻的衬底表面上。重掺杂区域被离子注入在外围部分中的栅极结构的相对侧上。电介质间隔物被回蚀到小于第一宽度的第二宽度。通过离子注入形成双重轻掺杂区域，该衬底在衬底的由间隔物回蚀刻暴露的区域中。三个轻掺杂区域也可以通过在栅极边缘处的第一注入，通过中间间隔物的第二植入物和间隔物回蚀后的第三植入物形成。

110. 发明授权

US06734510B2 Technique to mitigate short channel effects with vertical gate transistor with different gate materials 有权
公开(公告)号：US06734510B2
公开(公告)日：2004-05-11
申请号：US09808114
申请日：2001-03-15
申请人： Leonard Forbes , Luan C. Tran , Kie Y. Ahn
发明人： Leonard Forbes , Luan C. Tran , Kie Y. Ahn
IPC分类号： H01L29772
CPC分类号： H01L29/4983 , H01L21/28105 , H01L27/10873 , H01L29/7831
摘要： This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.

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