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101. 发明申请

US20050130383A1 SILICIDE RESISTOR IN BEOL LAYER OF SEMICONDUCTOR DEVICE AND METHOD 审中-公开
标题翻译：半导体器件的BEOL层中的硅化物电阻和方法
公开(公告)号：US20050130383A1
公开(公告)日：2005-06-16
申请号：US10707388
申请日：2003-12-10
申请人： Ramachandra Divakaruni , Jay Strane
发明人： Ramachandra Divakaruni , Jay Strane
IPC分类号： H01L21/02 , H01L21/20 , H01L27/08
CPC分类号： H01L28/24 , H01L27/0802
摘要： A suicide resistor for inclusion in a BEOL layer, and a method of forming the same that provides few additional manufacturing steps. The method allows formation of a passive resistor during BEOL processing without high temperature anneals that would damage other BEOL wiring structures. In particular, the method includes forming a silicide over a polysilicon base in a trough, where the silicide provides the desired resistivity and has a silicidation temperature less than a damaging temperature of the plurality of BEOL layers.
摘要翻译：用于包含在BEOL层中的自杀电阻器及其形成方法，其提供了少量附加的制造步骤。该方法允许在BEOL处理期间形成无源电阻，而不会导致其它BEOL布线结构的高温退火。特别地，该方法包括在槽中的多晶硅基底上形成硅化物，其中硅化物提供期望的电阻率并且具有小于多个BEOL层的破坏温度的硅化温度。

102. 发明申请

US20050026363A1 Method and structure for vertical dram devices with self-aligned upper trench shaping 失效
标题翻译：具有自对准上沟槽成形的垂直拉丝装置的方法和结构
公开(公告)号：US20050026363A1
公开(公告)日：2005-02-03
申请号：US10604565
申请日：2003-07-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , C.Y. Sung
发明人： Kangguo Cheng , Ramachandra Divakaruni , C.Y. Sung
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.
摘要翻译：半导体衬底中的存储单元的方法和结构包括在衬底中形成的深沟槽的下部形成掺杂剂源材料。沟槽的上部被成形为大致矩形的构造，并且掺杂剂源材料被退火以形成沟槽电容器的掩埋板。掩埋板与沟槽的成形上部自对准。

103. 发明授权

US06833305B2 Vertical DRAM punchthrough stop self-aligned to storage trench 失效
公开(公告)号：US06833305B2
公开(公告)日：2004-12-21
申请号：US10838018
申请日：2004-05-03
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

104. 发明授权

US06831006B2 Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner 失效
标题翻译：使用多晶硅衬垫消除金属接触P阱或N阱短路或高泄漏路径的结构和方法
公开(公告)号：US06831006B2
公开(公告)日：2004-12-14
申请号：US10345468
申请日：2003-01-15
申请人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
发明人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L27/10864 , H01L27/10888
摘要： A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.
摘要翻译：当接触通孔掩模与有源区域掩模不对准时，可能会发生从金属接触到P阱的短路或高泄漏路径，以及与隔离沟槽隔离氧化物的隔离结合，隔离沟槽在隔离层中形成阴极氧化物，暴露接触点耗尽区域或甚至暴露在有源区域侧壁上的P阱。通过使用N +掺杂多晶硅衬垫来防止这个问题，其中来自多层衬垫的N +掺杂剂的扩散在有源区硅中形成N +卤素延伸，从而在金属接触柱和P阱之间提供反向偏置的结。还公开了N阱和P +掺杂剂的互补结构和方法。

105. 发明授权

US06670667B2 Asymmetric gates for high density DRAM 失效
公开(公告)号：US06670667B2
公开(公告)日：2003-12-30
申请号：US10213061
申请日：2002-08-06
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

106. 发明授权

US06458646B1 Asymmetric gates for high density DRAM 失效
标题翻译：用于高密度DRAM的非对称门
公开(公告)号：US06458646B1
公开(公告)日：2002-10-01
申请号：US09608019
申请日：2000-06-30
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.
摘要翻译：一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。

107. 发明授权

US06455886B1 Structure and process for compact cell area in a stacked capacitor cell array 失效
标题翻译：叠层电容器阵列中紧凑单元面积的结构和工艺
公开(公告)号：US06455886B1
公开(公告)日：2002-09-24
申请号：US09636564
申请日：2000-08-10
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L29/66181
摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.
摘要翻译：一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。在半导体衬底中形成隔离区以隔离晶体管。在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。

108. 发明授权

US06440872B1 Method for hybrid DRAM cell utilizing confined strap isolation 失效
标题翻译：混合DRAM单元利用限制带隔离的方法
公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译：形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

109. 发明授权

US06420749B1 Trench field shield in trench isolation 失效
标题翻译：沟槽隔离屏蔽沟槽
公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译：一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。第一装置可以独立于第二装置而被偏置。接触件在衬底的表面上方延伸。第一接触件邻接第一器件和第一导电侧壁间隔物。绝缘体将导电侧墙隔离开。第一接触件可以在第一导体和第二导体之间等距。导电侧壁间隔件包括场屏蔽。

110. 发明授权

US06414347B1 Vertical MOSFET 失效
标题翻译：垂直MOSFET
公开(公告)号：US06414347B1
公开(公告)日：2002-07-02
申请号：US09790011
申请日：2001-02-09
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L21/2255 , H01L21/26586 , H01L27/10841 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
摘要翻译：一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

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