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1. 发明授权

US06831006B2 Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner 失效
标题翻译：使用多晶硅衬垫消除金属接触P阱或N阱短路或高泄漏路径的结构和方法
公开(公告)号：US06831006B2
公开(公告)日：2004-12-14
申请号：US10345468
申请日：2003-01-15
申请人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
发明人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L27/10864 , H01L27/10888
摘要： A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.
摘要翻译：当接触通孔掩模与有源区域掩模不对准时，可能会发生从金属接触到P阱的短路或高泄漏路径，以及与隔离沟槽隔离氧化物的隔离结合，隔离沟槽在隔离层中形成阴极氧化物，暴露接触点耗尽区域或甚至暴露在有源区域侧壁上的P阱。通过使用N +掺杂多晶硅衬垫来防止这个问题，其中来自多层衬垫的N +掺杂剂的扩散在有源区硅中形成N +卤素延伸，从而在金属接触柱和P阱之间提供反向偏置的结。还公开了N阱和P +掺杂剂的互补结构和方法。

2. 发明申请

US20050062133A1 Structure and method for eliminating metal contact to P-well of N-well shorts or high leakage paths using polysilicon liner 审中-公开
标题翻译：使用多晶硅衬垫消除N阱短路或高泄漏路径的P阱的金属接触的结构和方法
公开(公告)号：US20050062133A1
公开(公告)日：2005-03-24
申请号：US10969705
申请日：2004-10-20
申请人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
发明人： Ramachandra Divakaruni , Jack Mandelman , Haining Yang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/8242 , H01L29/00
CPC分类号： H01L21/76897 , H01L27/10864 , H01L27/10888
摘要： A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed
摘要翻译：当接触通孔掩模与有源区域掩模不对准时，可能会发生从金属接触到P阱的短路或高泄漏路径，以及与隔离沟槽隔离氧化物的隔离结合，隔离沟槽在隔离层中形成阴极氧化物，暴露接触点耗尽区域或甚至暴露在有源区域侧壁上的P阱。通过使用N +掺杂多晶硅衬垫来防止这个问题，其中来自多层衬垫的N +掺杂剂的扩散在有源区硅中形成N +卤素延伸，从而在金属接触柱和P阱之间提供反向偏置的结。还公开了N阱和P +掺杂剂的互补结构和方法

3. 发明申请

US20070045698A1 Semiconductor structures with body contacts and fabrication methods thereof 审中-公开
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US20070045698A1
公开(公告)日：2007-03-01
申请号：US11216395
申请日：2005-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

4. 发明申请

US20050167741A1 ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES 失效
标题翻译：垂直通道门和大气门逻辑门的封装间隔
公开(公告)号：US20050167741A1
公开(公告)日：2005-08-04
申请号：US10770264
申请日：2004-02-02
申请人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

5. 发明授权

US06509226B1 Process for protecting array top oxide 有权
标题翻译：保护阵列顶部氧化物的方法
公开(公告)号：US06509226B1
公开(公告)日：2003-01-21
申请号：US09670741
申请日：2000-09-27
申请人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
发明人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
摘要翻译：包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。沉积栅极堆叠并图案化，并且该工艺继续完成。

6. 发明申请

US20070189057A1 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 失效
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：US20070189057A1
公开(公告)日：2007-08-16
申请号：US11306749
申请日：2006-01-10
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

7. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

8. 发明申请

US20050145983A1 Structures and methods of anti-fuse formation in SOI 有权
公开(公告)号：US20050145983A1
公开(公告)日：2005-07-07
申请号：US11055106
申请日：2005-02-11
申请人： Claude Bertin , Ramachandra Divakaruni , Russell Houghton , Jack Mandelman , William Tonti
发明人： Claude Bertin , Ramachandra Divakaruni , Russell Houghton , Jack Mandelman , William Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L29/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

9. 发明授权

US06670667B2 Asymmetric gates for high density DRAM 失效
公开(公告)号：US06670667B2
公开(公告)日：2003-12-30
申请号：US10213061
申请日：2002-08-06
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

10. 发明授权

US06458646B1 Asymmetric gates for high density DRAM 失效
标题翻译：用于高密度DRAM的非对称门
公开(公告)号：US06458646B1
公开(公告)日：2002-10-01
申请号：US09608019
申请日：2000-06-30
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.
摘要翻译：一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。

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