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1. 发明授权

US06777737B2 Vertical DRAM punchthrough stop self-aligned to storage trench 有权
标题翻译：垂直DRAM穿透停止自对准到存储沟槽
公开(公告)号：US06777737B2
公开(公告)日：2004-08-17
申请号：US10016605
申请日：2001-10-30
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要翻译：具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。每个存储单元包括覆盖沟槽电容器的垂直晶体管。在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。

2. 发明授权

US06833305B2 Vertical DRAM punchthrough stop self-aligned to storage trench 失效
公开(公告)号：US06833305B2
公开(公告)日：2004-12-21
申请号：US10838018
申请日：2004-05-03
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

3. 发明授权

US06703274B1 Buried strap with limited outdiffusion and vertical transistor DRAM 有权
标题翻译：带有限制扩散和垂直晶体管DRAM的埋地带
公开(公告)号：US06703274B1
公开(公告)日：2004-03-09
申请号：US10336988
申请日：2003-01-03
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
IPC分类号： H02L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.
摘要翻译：具有垂直晶体管的DRAM单元通过在初始掩埋带扩散之前移动影响热预算的高温步骤而形成具有减小的横向扩展的埋地带外扩散。栅极导体形成为两个阶段，其中多个侧壁被放置在牺牲沟槽顶部氧化物之上，以在形成LDD延伸之前形成自对准多晶硅绝缘体结构。

4. 发明授权

US06573561B1 Vertical MOSFET with asymmetrically graded channel doping 失效
标题翻译：具有不对称梯度通道掺杂的垂直MOSFET
公开(公告)号：US06573561B1
公开(公告)日：2003-06-03
申请号：US10096192
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/1041 , H01L29/7827
摘要： Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.
摘要翻译：垂直MOSFET晶体管中的短沟道效应显着降低，在具有垂直非对称阈值注入的晶体管中，DRAM单元中的结漏电减少，其它器件参数不受影响。优选实施例具有将阈值注入的峰值从源极和漏极之间的中途的常规位置移动到不超过源极底部的沟道长度的三分之一的点。

5. 发明申请

US20060091442A1 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US20060091442A1
公开(公告)日：2006-05-04
申请号：US11298800
申请日：2005-12-09
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

6. 发明授权

US06787838B1 Trench capacitor DRAM cell using buried oxide as array top oxide 有权
标题翻译：沟槽电容器DRAM单元采用埋置氧化物作为阵列顶部氧化物
公开(公告)号：US06787838B1
公开(公告)日：2004-09-07
申请号：US10250259
申请日：2003-06-18
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Deok-kee Kim
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/1203
摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与基质。

7. 发明申请

US20050247966A1 OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
标题翻译：在SOI上用于eDRAM的盒式垂直晶体管
公开(公告)号：US20050247966A1
公开(公告)日：2005-11-10
申请号：US10709450
申请日：2004-05-06
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242 , H01L27/108 , H01L31/119
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

8. 发明授权

US07683428B2 Vertical Fin-FET MOS devices 有权
标题翻译：垂直Fin-FET MOS器件
公开(公告)号：US07683428B2
公开(公告)日：2010-03-23
申请号：US10597288
申请日：2004-01-22
申请人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
发明人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
IPC分类号： H01L27/108
CPC分类号： H01L29/78642 , H01L21/2257 , H01L29/66787
摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
摘要翻译：描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。盖板（24A，24B）沿翅片的侧壁形成。当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

9. 发明授权

US06724031B1 Method for preventing strap-to-strap punch through in vertical DRAMs 有权
标题翻译：用于防止在垂直DRAM中穿带穿过的方法
公开(公告)号：US06724031B1
公开(公告)日：2004-04-20
申请号：US10340999
申请日：2003-01-13
申请人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
发明人： Hiroyuki Akatsu , Dureseti Chidambarrao , Ramachandra Divakaruni , Jack Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.
摘要翻译：一种动态随机存取存储单元，包括：形成在硅衬底中的沟槽电容器; 在所述沟槽电容器上方的硅衬底中形成的垂直MOSFET，所述垂直MOSFET具有栅极电极，从所述硅衬底的表面延伸到所述硅衬底的第一源极/漏极区域，与所述第二源极/漏极区域电接触的第二源极/ 沟槽电容器，形成在第一源极/漏极区域和埋入的第二源极/漏极区域之间的硅衬底中的沟道区域和设置在栅极电极和沟道区域之间的栅极氧化物层; 第一源极/漏极区域也属于相邻的垂直MOSFET，相邻的垂直MOSFET具有电连接到相邻沟槽电容器的掩埋的第三源极/漏极区域，所述埋入的第二和第三源极/漏极区域彼此延伸; 以及设置在埋入的第二和第三源极/漏极区之间的穿通防止区域。

10. 发明申请

US20090200604A1 VERTICAL FIN-FET MOS DEVICES 有权
标题翻译：垂直熔池MOS器件
公开(公告)号：US20090200604A1
公开(公告)日：2009-08-13
申请号：US10597288
申请日：2004-01-22
申请人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
发明人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78642 , H01L21/2257 , H01L29/66787
摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
摘要翻译：描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。盖板（24A，24B）沿翅片的侧壁形成。当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

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