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101. 发明授权

US5926697A Method of forming a moisture guard ring for integrated circuit applications 失效
标题翻译：形成用于集成电路应用的防潮环的方法
公开(公告)号：US5926697A
公开(公告)日：1999-07-20
申请号：US947793
申请日：1997-10-09
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Jin-Yuan Lee , Hsien Wei Chin
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Jin-Yuan Lee , Hsien Wei Chin
IPC分类号： H01L21/02 , H01L21/761 , H01L23/525 , H01L21/76
CPC分类号： H01L28/87 , H01L21/761 , H01L23/5258 , H01L2924/0002
摘要： An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.
摘要翻译：已经开发了用于在具有至少一个级别的多晶硅布线的集成电路中形成保护环的改进和新的结构和方法。保护环形成，而不需要额外的制造工艺步骤，并且保护环结合到半导体衬底，从而为水分和污染物从绝缘层中的窗口扩散到半导体器件区域提供了优越的屏障。

102. 发明授权

US09356058B2 Backside structure for BSI image sensor 有权
标题翻译： BSI图像传感器的背面结构
公开(公告)号：US09356058B2
公开(公告)日：2016-05-31
申请号：US13597007
申请日：2012-08-28
申请人： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Keng-Yu Chou , Shuang-Ji Tsai , Min-Feng Kao
发明人： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Keng-Yu Chou , Shuang-Ji Tsai , Min-Feng Kao
IPC分类号： H01L21/311 , H01L27/146
CPC分类号： H01L27/1462 , H01L27/1464 , H01L27/14685
摘要： An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region.
摘要翻译：用于形成图像传感器的实施例方法包括在支撑光电二极管的半导体的表面上形成抗反射涂层，在抗反射涂层上形成蚀刻停止层，在蚀刻停止层上形成缓冲氧化物，并且选择性地去除通过蚀刻的缓冲氧化物的一部分，在蚀刻期间保护抗反射涂层的蚀刻停止层。一种实施方式的图像传感器包括：配置在阵列区域和外围区域中的半导体，支撑阵列区域中的光电二极管的半导体，设置在半导体表面上的抗反射涂层，在阵列区域中的光电二极管上的蚀刻停止层的厚度小于周边区域中的蚀刻停止层的厚度，以及设置在周边区域的蚀刻停止层上的缓冲氧化物。

103. 发明授权

US09318370B2 High-k dielectric liners in shallow trench isolations 有权
标题翻译：浅沟槽隔离中的高k电介质衬垫
公开(公告)号：US09318370B2
公开(公告)日：2016-04-19
申请号：US13198018
申请日：2011-08-04
申请人： Szu-Ying Chen , Tzu-Jui Wang , Jen-Cheng Liu , Dun-Nian Yaung
发明人： Szu-Ying Chen , Tzu-Jui Wang , Jen-Cheng Liu , Dun-Nian Yaung
IPC分类号： H01L27/14 , H01L21/762 , H01L27/146
CPC分类号： H01L27/1463 , H01L21/76232 , H01L27/14643 , H01L27/14689
摘要： A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.
摘要翻译：电路结构包括具有顶表面的半导体衬底。电介质材料从顶表面延伸到半导体衬底中。高k电介质层由高k电介质材料形成，其中高k电介质层包括电介质材料的侧壁上的第一部分和介电材料下面的第二部分。

104. 发明授权

US09153565B2 Image sensors with a high fill-factor 有权
标题翻译：具有高填充因子的图像传感器
公开(公告)号：US09153565B2
公开(公告)日：2015-10-06
申请号：US13486724
申请日：2012-06-01
申请人： Szu-Ying Chen , Meng-Hsun Wan , Tzu-Jui Wang , Dun-Nian Yaung , Jen-Cheng Liu
发明人： Szu-Ying Chen , Meng-Hsun Wan , Tzu-Jui Wang , Dun-Nian Yaung , Jen-Cheng Liu
IPC分类号： H01L27/146 , H01L25/00 , H01L21/768 , H01L25/18
CPC分类号： H01L25/50 , H01L21/76898 , H01L25/18 , H01L27/14609 , H01L27/14634 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected from the group consisting essentially of a reset transistor, a selector, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit.
摘要翻译：一种器件包括其中包括图像传感器的第一芯片和与第一芯片接合的第二芯片。第二芯片包括从基本上由复位晶体管，选择器，行选择器及其组合组成的组中选择的逻辑器件。逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。

105. 发明授权

US09142586B2 Pad design for backside illuminated image sensor 有权
标题翻译：背面照明图像传感器的垫设计
公开(公告)号：US09142586B2
公开(公告)日：2015-09-22
申请号：US12708167
申请日：2010-02-18
申请人： Wen-De Wang , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Jeng-Shyan Lin
发明人： Wen-De Wang , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Jeng-Shyan Lin
IPC分类号： H01L27/14 , H01L27/146
CPC分类号： H01L27/14636 , H01L23/481 , H01L27/14621 , H01L27/1464 , H01L27/14683
摘要： A semiconductor image sensor device includes first and second semiconductor substrates. A pixel array and a control circuit are formed in a first surface of the first substrate. An interconnect layer is formed over the first surface of the first substrate and electrically connects the control circuit to the pixel array. A top conducting layer is formed over the interconnect layer to have electrical connectivity with at least one of the control circuit or the pixel array via the interconnect layer. A surface of a second substrate is bonded to the top conducting layer. A conductive through-silicon-via (TSV) passes through the second substrate, and has electrical connectivity with the top conducting layer. A terminal is formed on an opposite surface of the second substrate, and electrically connected to the TSV.
摘要翻译：半导体图像传感器装置包括第一和第二半导体衬底。像素阵列和控制电路形成在第一基板的第一表面中。在第一基板的第一表面上形成互连层，并将控制电路电连接到像素阵列。顶部导电层形成在互连层上，以经由互连层与至少一个控制电路或像素阵列电连接。第二基板的表面接合到顶部导电层。导电硅通孔（TSV）通过第二衬底，并且与顶部导电层具有电连接性。端子形成在第二基板的相对表面上，并电连接到TSV。

106. 发明授权

US09040891B2 Image device and methods of forming the same 有权
标题翻译：图像装置及其形成方法
公开(公告)号：US09040891B2
公开(公告)日：2015-05-26
申请号：US13492348
申请日：2012-06-08
申请人： U-Ting Chen , Dun-Nian Yaung , Jen-Cheng Liu , Yu-Hao Shih , Chih-Chien Wang , Shih Pei Chou , Wei-Tung Huang , Cheng-Ta Wu
发明人： U-Ting Chen , Dun-Nian Yaung , Jen-Cheng Liu , Yu-Hao Shih , Chih-Chien Wang , Shih Pei Chou , Wei-Tung Huang , Cheng-Ta Wu
IPC分类号： H01L27/00 , H01L21/033 , H01L27/146
CPC分类号： H01L21/0334 , H01L21/0337 , H01L27/14603 , H01L27/1464 , H01L27/14689
摘要： A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.
摘要翻译：形成图像传感器装置的方法包括具有像素区域和周边区域的基板。在周边区域中蚀刻多个第一沟槽。每个第一沟槽具有深度D1。掩模层形成在衬底上。掩模层在像素区域中具有多个开口。间隔件形成在每个开口的内表面中。通过在像素区域中具有间隔物的每个开口蚀刻多个第二沟槽。每个第二沟槽具有深度D2。深度D1大于深度D2。

107. 发明授权

US08957358B2 CMOS image sensor chips with stacked scheme and methods for forming the same 有权
标题翻译：具有堆叠方案的CMOS图像传感器芯片及其形成方法
公开(公告)号：US08957358B2
公开(公告)日：2015-02-17
申请号：US13571184
申请日：2012-08-09
申请人： Meng-Hsun Wan , Szu-Ying Chen , Dun-Nian Yaung , Jen-Cheng Liu
发明人： Meng-Hsun Wan , Szu-Ying Chen , Dun-Nian Yaung , Jen-Cheng Liu
IPC分类号： H01L27/146
CPC分类号： H01L27/14634 , H01L27/14609 , H01L27/14636 , H01L27/1464 , H01L27/1469
摘要： A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.
摘要翻译：一种设备包括其中包括图像传感器的图像传感器芯片。一个读出的芯片是底层的，并粘贴到图像传感器芯片上。读出芯片包括从基本上由复位晶体管，源极跟随器，行选择器及其组合组成的组中选择的逻辑器件。逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。外围电路芯片是底层的，并与读出的芯片结合。外围电路芯片包括逻辑电路，穿透外围电路芯片的半导体衬底的贯通孔以及外围电路芯片底面的电连接器。电连接器通过通孔电耦合到外围电路芯片中的逻辑电路。

108. 发明授权

US08685820B2 Multiple gate dielectric structures and methods of forming the same 有权
标题翻译：多栅电介质结构及其形成方法
公开(公告)号：US08685820B2
公开(公告)日：2014-04-01
申请号：US13207643
申请日：2011-08-11
申请人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
发明人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
IPC分类号： H01L21/336
CPC分类号： H01L27/14614 , H01L27/14689
摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
摘要翻译：本公开提供了多栅极电介质半导体结构和形成这种结构的方法。在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

109. 发明授权

US08664736B2 Bonding pad structure for a backside illuminated image sensor device and method of manufacturing the same 有权
标题翻译：用于背面照明图像传感器装置的接合垫结构及其制造方法
公开(公告)号：US08664736B2
公开(公告)日：2014-03-04
申请号：US13112755
申请日：2011-05-20
申请人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Jeng-Shyan Lin , Wen-De Wang , Yueh-Chiou Lin
发明人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Jeng-Shyan Lin , Wen-De Wang , Yueh-Chiou Lin
IPC分类号： H01L27/146
CPC分类号： H01L23/5226 , H01L21/76898 , H01L27/14636 , H01L27/1464 , H01L27/14689 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a device substrate having a front side and a back side. The semiconductor device further includes an interconnect structure disposed on the front side of the device substrate, the interconnect structure having a n-number of metal layers. The semiconductor device also includes a bonding pad disposed on the back side of the device substrate, the bonding pad extending through the interconnect structure and directly contacting the nth metal layer of the n-number of metal layers.
摘要翻译：一种半导体器件，包括具有正面和背面的器件基板。半导体器件还包括设置在器件基板的前侧的互连结构，该互连结构具有n个金属层。半导体器件还包括设置在器件衬底的背面上的接合焊盘，焊盘延伸穿过互连结构并直接接触n个金属层的第n个金属层。

110. 发明授权

US08629524B2 Apparatus for vertically integrated backside illuminated image sensors 有权
标题翻译：用于垂直集成的背面照明图像传感器的装置
公开(公告)号：US08629524B2
公开(公告)日：2014-01-14
申请号：US13458812
申请日：2012-04-27
申请人： Tzu-Jui Wang , Szu-Ying Chen , Jen-Cheng Liu , Dun-Nian Yaung , Ping-Yin Liu , Lan-Lin Chao
发明人： Tzu-Jui Wang , Szu-Ying Chen , Jen-Cheng Liu , Dun-Nian Yaung , Ping-Yin Liu , Lan-Lin Chao
IPC分类号： H01L31/0232
CPC分类号： H01L27/14683 , H01L27/14618 , H01L27/14634 , H01L27/1469 , H01L2924/0002 , H01L2924/00
摘要： A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.
摘要翻译：背面照明图像传感器包括光电二极管和位于第一芯片中的第一晶体管，其中第一晶体管电耦合到光电二极管。背面照明图像传感器还包括形成在第二芯片中的第二晶体管和形成在第三芯片中的多个逻辑电路，其中第二芯片堆叠在第一芯片上，第三芯片堆叠在第二芯片上。逻辑电路，第二晶体管和第一晶体管通过多个焊盘和通孔彼此耦合。

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