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91. 发明申请

US20050122829A1 Low voltage detector and method for detecting low voltage of FeRAM, and system using the same 有权
公开(公告)号：US20050122829A1
公开(公告)日：2005-06-09
申请号：US11033762
申请日：2005-01-13
申请人： Hee Bok Kang
发明人： Hee Bok Kang
IPC分类号： G11C5/14 , G11C11/22 , G11C8/02
CPC分类号： G11C5/143 , G11C11/22
摘要： A low voltage detector and method of detecting low voltage of a nonvolatile memory chip is disclosed wherein a memory cell does not operate in a low voltage and definitly discriminate activation and deactivation voltage area of the chip by synchronizing operation start and stop points of a FeRAM cell to a chip enable signal according to variation of system power for safely operating the chip in threshold voltage region. In this way, because the chip safely operates even the threshold voltage region such as the on/off states of power voltage, the chip can be protected even at the on/off states of power voltage and the layout area of the chip becomes efficient without having additional circuits.

92. 发明申请

US20050117443A1 EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same 失效
标题翻译： EEPROM单元和EEPROM器件具有高集成度和低源电阻及其制造方法
公开(公告)号：US20050117443A1
公开(公告)日：2005-06-02
申请号：US10997835
申请日：2004-11-24
申请人： Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
发明人： Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
IPC分类号： H01L27/115 , G11C8/02 , H01L21/8247
CPC分类号： H01L27/11524 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.
摘要翻译：提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的衬底上。具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。在第一区域中，第一漏极区域和第二浮动区域彼此分开地形成。在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度杂质区。

93. 发明授权

US06890770B2 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件结构及其制造方法
公开(公告)号：US06890770B2
公开(公告)日：2005-05-10
申请号：US10885869
申请日：2004-07-06
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： G11C20060101 , G11C8/02 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/00 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

94. 发明授权

US06889357B1 Timing calibration pattern for SLDRAM 失效
公开(公告)号：US06889357B1
公开(公告)日：2005-05-03
申请号：US09568155
申请日：2000-05-10
申请人： Brent Keeth , Brian Johnson , Terry R. Lee , Paul M. Fuller
发明人： Brent Keeth , Brian Johnson , Terry R. Lee , Paul M. Fuller
IPC分类号： G11B27/00 , G11C7/10 , G11C8/02 , H03L7/081 , H04L7/00 , H04L7/04 , H04L7/10
CPC分类号： G11C7/222 , G11C7/1072 , G11C2207/2254 , H03L7/0812 , H04L7/0041 , H04L7/043 , H04L7/10
摘要： Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

95. 发明授权

US06882578B2 PCRAM rewrite prevention 有权
标题翻译： PCRAM重写预防
公开(公告)号：US06882578B2
公开(公告)日：2005-04-19
申请号：US10680161
申请日：2003-10-08
申请人： John Moore , R. Jacob Baker
发明人： John Moore , R. Jacob Baker
IPC分类号： G11C13/00 , G11C8/02 , G11C11/34 , G11C11/406 , G11C11/4091 , G11C13/02 , G11C16/02 , G11C16/28 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/406 , G11C11/4091 , G11C13/0011 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C2013/0054 , G11C2207/2281 , G11C2213/72 , G11C2213/76 , G11C2213/79
摘要： A programmable conductor memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the programmable contact memory cell has an access transistor, the access transistor is switched off to decouple the cell from the bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For programmable contact memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell. The isolation transistor, normally conducting, is switched off after the predetermined time past the time the bit line begins to discharge through the programmable contact memory cell, thereby isolating the programmable contact memory cell from the sense amplifier before a sensing operation begins.
摘要翻译：可编程导体存储单元由读出放大器读取，但不重写存储单元的内容。如果可编程触点存储单元具有存取晶体管，则在预定的时间量之后，存取晶体管被切断以将该单元与位线去耦。预定的时间量足够长以允许将单元的逻辑状态传送到位线，并且还足够短以在读出放大器操作之前将单元与位线隔离。对于不使用存取晶体管的可编程触点存储单元，可以将隔离晶体管放置在位线之间，位线之间并且串行连接从读出放大器到隔离晶体管的位线的部分，隔离晶体管到存储单元。在通过可编程触点存储单元的位线开始放电的时间之后的预定时间之后，正常导通的隔离晶体管被关断，从而在感测操作开始之前将可编程触点存储单元与读出放大器隔离。

96. 发明申请

US20050073900A1 Reduced signal swing in bit lines in a CAM 有权
标题翻译：降低CAM中位线中的信号摆幅
公开(公告)号：US20050073900A1
公开(公告)日：2005-04-07
申请号：US10982892
申请日：2004-11-08
申请人： Zvi Regev
发明人： Zvi Regev
IPC分类号： G11C15/04 , G11C8/02
CPC分类号： G11C15/04
摘要： A Content Addressable Memory device with a bit line that is driven between first and second voltage levels depending on the state of a logic signal applied thereto. The magnitude of the voltage swing between the first and second voltage levels is reduced in comparison to other voltages of the Content Addressable Memory device, or in comparison to the voltage swing of prior art bit lines, so that effects associated with power dissipation by the bit line are reduced. The memory includes a plurality of match lines and a plurality of bit lines, each of the plurality of bit lines coupled to a bit line driver circuit adapted to provide a bit line voltage with reduced signal swing.
摘要翻译：一种内容可寻址存储器件，具有根据施加到其上的逻辑信号的状态在第一和第二电压电平之间驱动的位线。与内容可寻址存储器件的其他电压相比，或者与现有技术位线的电压摆幅相比，第一和第二电压电平之间的电压摆幅的幅度减小，使得与位的功率耗散相关联的效应线减少。所述存储器包括多个匹配线和多个位线，所述多个位线中的每一个耦合到位线驱动器电路，所述位线驱动电路适于提供具有减小的信号摆幅的位线电压。

97. 发明申请

US20050062062A1 One-time programmable, non-volatile field effect devices and methods of making same 失效
标题翻译：一次性可编程，非易失性场效应器件及其制作方法
公开(公告)号：US20050062062A1
公开(公告)日：2005-03-24
申请号：US10864572
申请日：2004-06-09
申请人： Claude Bertin , Thomas Rueckes , Brent Segal , Bernhard Vogeli , Darren Brock , Venkatachalam Jaiprakash
发明人： Claude Bertin , Thomas Rueckes , Brent Segal , Bernhard Vogeli , Darren Brock , Venkatachalam Jaiprakash
IPC分类号： G11C7/06 , G11C8/02 , G11C11/00 , G11C11/50 , G11C13/02 , G11C16/02 , G11C16/04 , G11C17/16 , G11C23/00 , H01H59/00 , H01J1/62 , H01L20060101 , H01L21/336 , H01L21/82 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L27/28 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/76 , H01L51/00 , H01L51/05 , H01L51/30 , H03K17/16
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate has a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically coupled to one of the source, drain and gate and has an electromechanically-deflectable nanotube element that is positioned to be deflectable in response to electrical stimulation to form a non-volatile closed electrical state between the one of the source, drain and gate and its corresponding terminal.
摘要翻译：一次性可编程，非易失性场效应器件及其制作方法。在一个实施例中，一次性可编程的非易失性场效应器件包括源极，漏极和栅极，源极和漏极之间具有场可调整通道。源极，漏极和栅极中的每一个具有相应的端子。电机械可偏转的纳米管开关元件电耦合到源极，漏极和栅极中的一个，并且具有可机电偏转的纳米管元件，其被定位成响应于电刺激而可偏转以在第二电极之间形成非易失性闭合电状态源，漏，门之一及其相应的终端。

98. 发明申请

US20050047258A1 Robotic Data Storage Library With Soft Power On/Off Capability 有权
标题翻译：具有软电源开/关功能的机器人数据存储库
公开(公告)号：US20050047258A1
公开(公告)日：2005-03-03
申请号：US10604971
申请日：2003-08-28
申请人： Matthew Starr , Michael Goberis , Kenneth Lau
发明人： Matthew Starr , Michael Goberis , Kenneth Lau
IPC分类号： G06F20060101 , G11B17/22 , G11C8/02
CPC分类号： G11B17/228
摘要： A robotic data storage library with soft power on/off capability and a method for providing soft power capability in a robotic data storage library are disclosed. The method and apparatus control the application of power to at least one component of a robotic data storage library to reduce issues caused by transitioning the library between an ON state and an OFF state. One embodiment of a robotic data storage library, for example, comprises: (a) a plurality of storage locations, each capable of holding at least one data storage element; (b) a data transfer interface for receiving a data storage element and establishing a communication path with a data storage element so that data can be transferred between the data storage element and a host computer; (c) a transport unit for moving a data storage element between one of the plurality of storage locations and the data transfer interface; (d) a power supply for providing power to a component of the library; (e) a power switch switchable between an ON state and an OFF state; and (f) a power controller for monitoring the power switch for a transition between the ON state and the OFF state and after detecting a transition of the power switch between the ON state and the OFF state, controlling the application of power to the component.
摘要翻译：公开了一种具有软启动/关闭能力的机器人数据存储库以及在机器人数据存储库中提供软功率能力的方法。该方法和装置控制对机器人数据存储库的至少一个组件的功率的应用，以减少在导通状态和OFF状态之间转换库所引起的问题。例如，机器人数据存储库的一个实施例包括：（a）多个存储位置，每个存储位置能够保持至少一个数据存储元件; （b）数据传输接口，用于接收数据存储元件并建立与数据存储元件的通信路径，以便数据可以在数据存储元件与主计算机之间传送; （c）用于在所述多个存储位置之一和所述数据传送接口之间移动数据存储元件的传送单元; （d）为图书馆的一个组件提供电力的电源; （e）可在ON状态和OFF状态之间切换的电源开关; 以及（f）功率控制器，用于在ON状态和OFF状态之间转换并且在检测到ON状态和OFF状态之间的电力开关转换之后监视电源开关，控制对组件的电力的施加。

99. 发明申请

US20050036398A1 Synchronous first-in/first-out block memory for a field programmable gate array 有权
公开(公告)号：US20050036398A1
公开(公告)日：2005-02-17
申请号：US10948010
申请日：2004-09-22
申请人： Daniel Elftmann , Theodore Speers , Arunangshu Kundu
发明人： Daniel Elftmann , Theodore Speers , Arunangshu Kundu
IPC分类号： H03K19/177 , G11C8/02
CPC分类号： H03K19/1776 , H03K19/1778
摘要： The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

100. 发明申请

US20050036390A1 Non-volatile memory and non-volatile memory data rewriting method 有权
标题翻译：非易失性存储器和非易失性存储器数据重写方法
公开(公告)号：US20050036390A1
公开(公告)日：2005-02-17
申请号：US10484322
申请日：2002-07-19
申请人： Mitsuru Nakada , Mitsuhiko Tomita
发明人： Mitsuru Nakada , Mitsuhiko Tomita
IPC分类号： G06F11/14 , G11B20/18 , G11C16/10 , G11C8/02
CPC分类号： G11C16/105 , G06F11/1441 , G11B20/18 , G11C16/102
摘要： A nonvolatile memory and a data rewriting method of the nonvolatile memory that can readily detect a state of operation at a time of a system failure due to a power failure or the like and quickly and reliably restore the nonvolatile memory to a normal storage state by a simple method. In the nonvolatile memory including a physical block as a storage unit, the physical block having a data area (1) and a redundant area (2), the redundant area (2) includes: a logical block address storing area (3) for storing an address of a corresponding logical block; a previously used physical block address storing area (4) for storing an address of a physical block to be erased; and a status information storing area (6) for storing status information for distinguishing a state of operation in each stage occurring in performing data rewriting operation on the physical block.
摘要翻译：非易失性存储器和非易失性存储器的数据重写方法，其可以容易地检测由于电源故障等而导致的系统故障时的操作状态，并且通过以下方式快速可靠地将非易失性存储器恢复到正常存储状态简单的方法。在包括作为存储单元的物理块的非易失性存储器中，具有数据区（1）和冗余区（2）的物理块，冗余区（2）包括：逻辑块地址存储区（3），用于存储相应逻辑块的地址; 先前使用的物理块地址存储区域（4），用于存储要被擦除的物理块的地址; 以及状态信息存储区域（6），用于存储用于区分在物理块上执行数据重写操作时发生的每个阶段的操作状态的状态信息。

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