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    • 2. 发明授权
      US06662304B2 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 有权
    • Method and apparatus for bit-to-bit timing correction of a high speed memory bus
    • US06662304B2
    • 2003-12-09
    • US10046944
    • 2002-01-14
    • Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
    • Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
    • G06F112
    • G06F5/06 , G06F2205/102
    • A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit Each of the final phase command signals adjusts the phase of clock signal applied to the associated latch relative to the digital signal applied to the latch so that the digital signal is successfully captured responsive to the clock signal.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US06374360B1 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 有权
    • Method and apparatus for bit-to-bit timing correction of a high speed memory bus
    • 用于高速存储器总线的位对位定时校正的方法和装置
    • US06374360B1
    • 2002-04-16
    • US09209587
    • 1998-12-11
    • Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
    • Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
    • G06F112
    • G06F5/06 , G06F2205/102
    • A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits applies respective internal clock signals to respective latches in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit. Each of the final phase command signals adjusts the phase of clock signal applied to the associated latch relative to the digital signal applied to the latch so that the digital signal is successfully captured responsive to the clock signal.
    • 同步电路对应用于分组化存储器件的数字信号分组中的相应数字信号执行位对位定时校正。 每个数字信号包包括施加到相应锁存器的多个数字信号。 时钟发生器电路响应于外部时钟信号产生多个内部时钟信号，每个内部时钟信号具有相对于外部时钟信号的对应相位。 多个选择电路响应于相位指令信号将相应的内部时钟信号施加到相应的锁存器。 评估电路接收顺序地存储在所选择的一个锁存器中的数字信号，并产生指示每个数字信号是否具有期望值的结果信号。 控制电路顺序地选择锁存器并对每个所选择的锁存器进行操作，以调整施加到与所选择的锁存器相连的选择电路的相位指令信号，并存储针对每个相位指令信号从评估电路顺序接收的各个结果信号。 控制电路从存储的结果信号产生最终的相位指令信号，并将每个最终相位命令信号施加到相应的选择电路。 每个最终相位指令信号相对于施加到锁存器的数字信号调整施加到相关联的锁存器的时钟信号的相位，使得响应于时钟信号成功捕获数字信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明申请
      US20090141571A1 Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM 有权
    • Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM
    • 用于在高速DRAM中初始化读延迟跟踪电路的方法和装置
    • US20090141571A1
    • 2009-06-04
    • US12329779
    • 2008-12-08
    • James Brian Johnson , Brent Keeth , Feng Dan Lin
    • James Brian Johnson , Brent Keeth , Feng Dan Lin
    • G11C7/00 , G11C8/18 , G11C8/00
    • G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4072 , G11C11/4076 , G11C2207/2254 , H03L7/0812 , H03L7/095
    • A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
    • 控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。 值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L） 减去同步（SP）开销。 产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。 启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。 响应于读取命令来保持第二计数器的值。 将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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