专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20020178202A1 Floating point multiplier for delimited operands 有权
标题翻译：用于定界操作数的浮点乘数
公开(公告)号：US20020178202A1
公开(公告)日：2002-11-28
申请号：US10035674
申请日：2001-12-28
申请人： Sun Microsystems, Inc.
发明人： Guy L. Steele JR.
IPC分类号： G06F007/44
CPC分类号： G06F7/74 , G06F5/012 , G06F5/015 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
摘要翻译：一种用于提供与本发明一致的浮点乘积的方法包括使用多个中间级乘以精确度较小的操作数和非精确度的操作数。该方法还包括通过利用补偿求和来执行结合多个中间级中的一个的操作来校正由亚精度操作数引入的误差。

92. 发明申请

US20020178200A1 Circuit for selectively providing maximum or minimum of a pair of floating point operands 有权
公开(公告)号：US20020178200A1
公开(公告)日：2002-11-28
申请号：US10035746
申请日：2001-12-28
申请人： Sun Microsystems, Inc.
发明人： Guy L. Steele JR.
IPC分类号： G06F007/38 , G06F007/00
CPC分类号： G06F7/4876 , G06F5/012 , G06F5/015 , G06F7/44 , G06F7/483 , G06F7/4873 , G06F7/49905 , G06F7/544 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

93. 发明申请

US20020178199A1 Floating point status information testing circuit 有权
标题翻译：浮点状态信息测试电路
公开(公告)号：US20020178199A1
公开(公告)日：2002-11-28
申请号：US10035741
申请日：2001-12-28
申请人： Sun Microsystems, Inc.
发明人： Guy L. Steele JR.
IPC分类号： G06F007/38
CPC分类号： G06F7/483 , G06F5/012 , G06F5/015 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.
摘要翻译：浮点运算测试电路包括分析电路和耦合到分析电路的结果发生器电路。分析电路根据操作数内的数据确定浮点操作数的状态。操作数缓冲器可以将操作数提供给分析电路。结果生成器电路响应于至少一个控制信号，并且如果浮点分析电路将浮点状态与由控制信号指定的预定格式相匹配，则确定结果信号。结果信号可以调节浮点指令的结果。当测试不同格式的单个操作数时，结果生成器也可以响应多个控制信号，例如非数字（NaN），无限大，归一化，非归一化，无效操作，溢出，下溢，除零，精确，和不精确。

94. 发明申请

US20020178197A1 System and method for generating an integer part of a logarithm of a floating point operand 有权
标题翻译：用于生成浮点运算数对数的整数部分的系统和方法
公开(公告)号：US20020178197A1
公开(公告)日：2002-11-28
申请号：US10035585
申请日：2001-12-28
申请人： Sun Microsystems, Inc.
发明人： Guy L. Steele JR.
IPC分类号： G06F007/38
CPC分类号： G06F5/012 , G06F5/015 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F7/556 , G06F9/30014 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result. A result is assembled equaling the integer part of the logarithm of the floating point operand based on the at least one signal wherein, if the floating point operand is in at least one of a denormalized format, a normalized non-zero format, and a delimited format, an exponent field of the result equals the exponent field of the intermediate result and a fraction field high part of the result equals the fraction field high part of the intermediate result.
摘要翻译：根据本发明的实施例，对数单元计算浮点操作数的对数的整数部分。对数单位分析浮点运算数的格式，并产生代表格式的至少一个信号。对数单元基于至少一个信号来确定浮点操作数的无偏指数的大小作为中间结果，其中无偏指数由无偏指数位表示。此外，对数单元确定中间结果的指数字段和分数字段高部分。基于至少一个信号组合等于浮点操作数的对数的整数部分的结果，其中如果浮点操作数处于非归一化格式，归一化非零格式和定界中的至少一个中格式，结果的指数字段等于中间结果的指数字段，结果的分数字段高部分等于中间结果的分数字段高部分。

95. 发明授权

US6101516A Normalization shift prediction independent of operand subtraction 有权
标题翻译：归一化移位预测独立于操作数减法
公开(公告)号：US6101516A
公开(公告)日：2000-08-08
申请号：US191143
申请日：1998-11-13
申请人： Gilbert M. Wolrich , Timothy C. Fischer , John J. Ellis
发明人： Gilbert M. Wolrich , Timothy C. Fischer , John J. Ellis
IPC分类号： G06F5/01 , G06F7/50 , G06F7/57
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3884 , G06F7/4873 , G06F7/49952 , G06F7/49957
摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要翻译：描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道中的舍入加法器舞台操作。舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

96. 发明授权

US6061781A Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide 失效
标题翻译：并行执行浮点单位的分割微指令和整数除法的整数单位的溢出检测微指令
公开(公告)号：US6061781A
公开(公告)日：2000-05-09
申请号：US108945
申请日：1998-07-01
申请人： Dinesh K. Jain , Albert J. Loper, Jr. , Arturo Martin-de-Nicolas
发明人： Dinesh K. Jain , Albert J. Loper, Jr. , Arturo Martin-de-Nicolas
IPC分类号： G06F7/52 , G06F7/535 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/3017 , G06F9/3861 , G06F7/4873 , G06F7/4991
摘要： An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.
摘要翻译：提供了一种用于在微处理器中执行整数除法的装置和方法。该装置包括翻译逻辑，浮点执行逻辑和整数执行逻辑。翻译逻辑将整数除法指令解码为整数除法微指令序列和溢出检测微指令序列。整数除法微指令序列被路由到并由浮点执行逻辑执行。溢出检测微指令序列被路由到并由整数执行逻辑执行。整数执行逻辑和浮点执行逻辑同时执行溢出检测微指令序列和整数除微指令序列。

97. 发明授权

US5956263A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5956263A
公开(公告)日：1999-09-21
申请号：US797653
申请日：1997-01-31
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

98. 发明授权

US5867407A Normalization shift prediction independent of operand substraction 失效
标题翻译：归一化移位预测独立于操作数减法
公开(公告)号：US5867407A
公开(公告)日：1999-02-02
申请号：US955087
申请日：1997-10-21
申请人： Gilbert M. Wolrich , Timothy C. Fischer , John J. Ellis
发明人： Gilbert M. Wolrich , Timothy C. Fischer , John J. Ellis
IPC分类号： G06F5/01 , G06F7/50 , G06F7/57
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3884 , G06F7/4873 , G06F7/49952 , G06F7/49957
摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要翻译：描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道的舍入加法器舞台操作。舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

99. 发明授权

US5694350A Rounding adder for floating point processor 失效
标题翻译：用于浮点处理器的舍入加法器
公开(公告)号：US5694350A
公开(公告)日：1997-12-02
申请号：US497014
申请日：1995-06-30
申请人： Gilbert M. Wolrich , Timothy C. Fischer , John A. Kowaleski, Jr.
发明人： Gilbert M. Wolrich , Timothy C. Fischer , John A. Kowaleski, Jr.
IPC分类号： G06F7/50 , G06F7/52 , G06F7/535 , G06F7/57
CPC分类号： G06F7/535 , G06F7/485 , G06F7/57 , G06F2207/3824 , G06F2207/3884 , G06F7/4873 , G06F7/49915 , G06F7/49936 , G06F7/49952 , G06F7/49957
摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要翻译：描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道中的舍入加法器舞台操作。舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

100. 发明授权

US5309383A Floating-point division circuit 失效
标题翻译：浮点分割电路
公开(公告)号：US5309383A
公开(公告)日：1994-05-03
申请号：US946316
申请日：1992-11-09
申请人： Koichi Kuroiwa
发明人： Koichi Kuroiwa
IPC分类号： G06F7/537 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/535 , G06F7/38
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/4873
摘要： A floating-point division circuit for performing division on floating-point data using a non-recovery type division method is disclosed. The floating-point division circuit includes a circuit portion for conducting a pre-division processing and pattern determination on a dividend and a divisor, an exponent operation portion, a mantissa division portion, and a quotient generating portion, further including either or both of an exception/non-operation detecting portion and a control portion. The exception/non-operation detecting portion generates a stop signal when detecting a non-operation pattern so as to stop a repetition of operations in the mantissa division portion. The control portion generates either a non-executional signal or a control signal so as to stop a latch operation during a period when no instruction for division is executed.
摘要翻译： PCT No.PCT / JP92 / 00296 Sec。 371日期：1992年11月9日 102（e）日期1992年11月9日PCT 1992年3月12日PCT公布。 WO92 / 16892 PCT出版物 1992年10月1日公开了一种使用非恢复型分割方法对浮点数据进行分割的浮点分割电路。浮点分割电路包括用于对除数和除数进行预分割处理和图案确定的电路部分，指数运算部分，尾数分割部分和商产生部分，还包括以下任一或两者：异常/非操作检测部分和控制部分。异常/非操作检测部分在检测非操作模式时产生停止信号，以停止尾数分割部分中的操作的重复。控制部分产生非执行信号或控制信号，以便在不执行分割指令的时段期间停止锁存操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式