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91. 发明授权

US06425070B1 Variable length instruction decoder 失效
标题翻译：可变长度指令解码器
公开(公告)号：US06425070B1
公开(公告)日：2002-07-23
申请号：US09044086
申请日：1998-03-18
申请人： Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
发明人： Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
IPC分类号： G06F9302
CPC分类号： G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.
摘要翻译：本发明是用于数字信号处理的新颖且改进的方法和电路。本发明的一个方面要求使用可变长度指令集。可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。

92. 发明申请

US20020087821A1 VLIW computer processing architecture with on-chip DRAM usable as physical memory or cache memory 审中-公开
标题翻译：具有片上DRAM的VLIW计算机处理架构可用作物理存储器或高速缓冲存储器
公开(公告)号：US20020087821A1
公开(公告)日：2002-07-04
申请号：US09802017
申请日：2001-03-08
发明人： Ashley Saulsbury , Nyles Nettleton , Michael Parkin , David R. Emberson
IPC分类号： G06F012/00
CPC分类号： G06F12/0802 , G06F15/7857 , G06F2212/2515 , G06F2212/601
摘要： According to the invention, a first processor chip (10) comprising a processing core (12) and at least one bank of memory (14). The at least one bank of memory (14) preferably includes a mode control input (32) for controlling the mode of the at least one bank of memory (14) between physical memory and cache memory. In addition, the first processor chip (10) may further comprise an I/O link (26) configured to facilitate communication between the first processor chip (10) and other processor chips, and a communication and memory controller (20, 22) in electrical communication with the processing core (12), the at least one bank of memory (14), and the I/O link (26). The communication and memory controller (20, 22) preferably controls the exchange of data between the first processor chip (10) and the other processor chips, as well as receive memory requests from the processing core (12) of the first processor chip (10) and from other processing cores residing on the other processor chips, and process the memory requests with the at least one bank of memory (14). The memory requests from the other processing cores on the other processor chips preferably are received by the first processor chip (10) through the I/O link (26).
摘要翻译：根据本发明，包括处理核心（12）和至少一个存储器组（14）的第一处理器芯片（10）。存储器（14）的至少一组优选地包括用于控制物理存储器和高速缓冲存储器之间的至少一组存储器（14）的模式的模式控制输入（32）。另外，第一处理器芯片（10）还可以包括被配置为促进第一处理器芯片（10）和其他处理器芯片之间的通信的I / O链路（26），以及通信和存储器控制器（20,22）与处理核心（12），至少一个存储器组（14）和I / O链路（26）的电通信。通信和存储器控制器（20,22）优选地控制第一处理器芯片（10）和其他处理器芯片之间的数据交换，以及从第一处理器芯片（10）的处理核心（12）接收存储器请求）和驻留在其他处理器芯片上的其他处理核心，并且与至少一个存储器组（14）处理存储器请求。优选地，来自其他处理器芯片上的其他处理核的存储器请求由第一处理器芯片（10）通过I / O链路（26）接收。

93. 发明申请

US20020063642A1 SOUND PROCESSING SYSTEM 失效
标题翻译：声音处理系统
公开(公告)号：US20020063642A1
公开(公告)日：2002-05-30
申请号：US09994650
申请日：2001-11-28
发明人： Kengo Maeda , Tomoyuki Kawai
IPC分类号： H03M001/00
CPC分类号： G10L15/28 , G06F15/7857 , G10L13/04
摘要： A signal processing system includes an A/D conversion section for converting an analog signal into a digital signal; a digital signal processing section for processing the digital signal; a D/A conversion section for converting the digital signal into an analog signal; a control section; and a memory section including a first program memory area for storing a program for processing the digital signal and a first data memory area. The digital signal processing section includes a second program memory area connected, via a first bus, to the first program memory area, and a second data memory area connected to the first data memory area via a second bus.
摘要翻译：信号处理系统包括用于将模拟信号转换为数字信号的A / D转换部分; 数字信号处理部分，用于处理数字信号; D / A转换部分，用于将数字信号转换为模拟信号; 控制部分; 以及存储部，包括用于存储用于处理数字信号的程序的第一程序存储区和第一数据存储区。数字信号处理部分包括经由第一总线连接到第一程序存储区域的第二程序存储器区域和经由第二总线连接到第一数据存储区域的第二数据存储区域。

94. 发明申请

US20010052047A1 Integrated circuit for modem 审中-公开
标题翻译：调制解调器集成电路
公开(公告)号：US20010052047A1
公开(公告)日：2001-12-13
申请号：US09873649
申请日：2001-06-04
申请人： NEC Corporation
发明人： Mitsuhiro Ono
IPC分类号： G06F012/08
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0851 , G06F12/1045 , G06F15/7846 , G06F15/7857
摘要： To reduce the circuit area and cost of the integrated circuit for modem. The RAM controller 5 performs such a control that the instructions are prefetched from the external instruction ROM to the instruction RAM 2 on a bank basis and the instruction RAM 2 is caused to operate as a cache memory for the external instruction ROM and the CPU and the hardware unit 1 are caused to the time-divisionally share part of banks of the instruction RAM 2.
摘要翻译：降低调制解调器集成电路的电路面积和成本。 RAM控制器5执行这样的控制，使得指令从外部指令ROM预取到基于存储体的指令RAM2，并且使指令RAM2作为用于外部指令ROM和CPU的高速缓存存储器和硬件单元1被分时地共享指令RAM 2的一部分。

95. 发明授权

US06282631B1 Programmable RISC-DSP architecture 有权
标题翻译：可编程RISC-DSP架构
公开(公告)号：US06282631B1
公开(公告)日：2001-08-28
申请号：US09220158
申请日：1998-12-23
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： G06F1500
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/34 , G06F9/345 , G06F9/3455 , G06F9/3879 , G06F15/7857
摘要： The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.
摘要翻译：本发明提供一种能够实现高效数字信号处理的音频信号处理器及其操作方法。快速乘法累加（MAC）和矢量处理能力在RISC架构中实现，为数字信号处理系统的高速能力提供了RISC处理器的速度和效率。

96. 发明授权

US06230235B1 Address lookup DRAM aging 有权
标题翻译：地址查找DRAM老化
公开(公告)号：US06230235B1
公开(公告)日：2001-05-08
申请号：US09163074
申请日：1998-09-29
申请人： Hsuehchung Shelton Lu , David Keene
发明人： Hsuehchung Shelton Lu , David Keene
IPC分类号： G06F1200
CPC分类号： G06F9/5016 , G06F12/0215 , G06F15/7857 , G11C11/406
摘要： Systems and methods are described for network address lookup entry aging in a DRAM memory. A method of DRAM data aging includes: refreshing a row of memory cells in an array of DRAM memory cells. The refreshing periodically includes aging all entries that are stored in the row of memory cells. The systems and methods provide advantages in that an existing operation is used for an additional function. In addition, the aging can be implemented with closely coupled logic using the sense amplifiers.
摘要翻译：描述了DRAM存储器中的网络地址查找条目老化的系统和方法。 DRAM数据老化的方法包括：刷新DRAM存储器单元阵列中的一行存储器单元。刷新周期性地包括老化存储在存储单元行中的所有条目。这些系统和方法提供了一个优点，即现有操作用于附加功能。此外，可以使用感测放大器使用紧密耦合的逻辑来实现老化。

97. 发明授权

US06175881B1 Microcontroller having a memory, a dedicated multitask memory, and switching circuit for selectively connecting the multitask memory to the internal or external bus 失效
标题翻译：具有存储器的微控制器，专用多任务存储器和用于选择性地将多任务存储器连接到内部或外部总线的切换电路
公开(公告)号：US06175881B1
公开(公告)日：2001-01-16
申请号：US09038836
申请日：1998-03-12
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F1310
CPC分类号： G06F15/7857
摘要： A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.
摘要翻译：一种微控制器，包括CPU1用于执行算术运算的第一存储器2; 用于在CPU1的运算处理期间存储从外部设备30传送的数据的多任务处理的第二存储器3; 总线开关4和5用于切换CPU1和外部设备30的数据总线的连接; 以及地址供应部分7，其连接到外部设备30的地址总线，同时第二存储器3连接到外部设备30的数据总线，并且产生用于存储来自外部设备的数据的地址信号，其中该微控制器可以执行多任务处理而不采用昂贵的设备，例如双端口RAM。

98. 发明授权

US6138136A Signal processor 有权
标题翻译：信号处理器
公开(公告)号：US6138136A
公开(公告)日：2000-10-24
申请号：US11673
申请日：1998-10-23
申请人： Harald Bauer , Dietmar Lorenz , Peter Meyer , Roberto Woudsma
发明人： Harald Bauer , Dietmar Lorenz , Peter Meyer , Roberto Woudsma
IPC分类号： G06F17/10 , G06F15/78 , G06F7/38
CPC分类号： G06F15/7857
摘要： A signal processor includes at least one data source (3), a plurality of input registers (11, 12, 13, 14, . . . ) whose inputs are coupled to the data source by data buses (9, 10), a plurality of multipliers (19, 20; 71, 72 . . . ) for multiplying data buffered in the input registers, and a processing arrangement spread over a plurality of data processor branches (4-0, 4-1, . . . , 4-N) for processing products (p0, p1, . . . ), generated by the multipliers by arithmetic and/or logic operations. For achieving enhanced flexibility of the signal processor and increasing the number of possible applications, multiplexers (15, 16, 17, 18; 70) are provided which are used for coupling the multipliers to a respective part of the input registers in dependence on control signals (I, II, III, IV). Such a signal processor is preferably used in mobile radio technology. Further fields of application are, for example, audio, video, medical and automotive technology, ISDN systems, and digital radio.
摘要翻译： PCT No.PCT / IB97 / 00760 Sec。 371 1998年10月23日第 102（e）日期1998年10月23日PCT提交1997年6月23日PCT公布。公开号WO97 / 50030 日期1997年12月31日信号处理器包括至少一个数据源（3），多个输入寄存器（11,12,13,14，...，...），其输入通过数据总线（9， 10），用于乘以在输入寄存器中缓冲的数据的多个乘法器（19,20; 71,72 ...）和分布在多个数据处理器分支（4-0，4-1，...）上的处理装置。 ...，4-N），用于通过算术和/或逻辑运算来生成由乘法器产生的乘积（p0，p1，...）。为了实现增强的信号处理器的灵活性并增加可能的应用的数量，提供多路复用器（15,16,17,18; 70），其用于根据控制信号将乘法器耦合到输入寄存器的相应部分（I，II，III，IV）。这样的信号处理器优选地用于移动无线电技术中。其他应用领域是例如音频，视频，医疗和汽车技术，ISDN系统和数字无线电。

99. 发明授权

US6104658A Distributed DRAM refreshing 有权
标题翻译：分布式DRAM刷新
公开(公告)号：US6104658A
公开(公告)日：2000-08-15
申请号：US162943
申请日：1998-09-29
申请人： Hsuehchung Shelton Lu
发明人： Hsuehchung Shelton Lu
IPC分类号： G06F9/50 , G06F12/02 , G06F15/78 , G11C11/406 , G11C7/00 , G11C8/00
CPC分类号： G06F12/0215 , G06F15/7857 , G06F9/5016 , G11C11/406
摘要： Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.
摘要翻译：描述了用于分布式DRAM刷新的系统和方法。分布式DRAM刷新的方法包括：用第一行读出放大器刷新DRAM存储单元的第一阵列中的第一行存储单元; 然后用第二行读出放大器刷新DRAM存储单元的第二阵列中的第二行存储单元。这些系统和方法提供了能够降低功率瞬变（噪声）的大小的优点。此外，当阵列被布置在多个子组中时，可以提高性能。

100. 发明授权

US5898892A Computer system with a data cache for providing real-time multimedia data to a multimedia engine 失效
标题翻译：具有用于向多媒体引擎提供实时多媒体数据的数据高速缓存的计算机系统
公开(公告)号：US5898892A
公开(公告)日：1999-04-27
申请号：US650941
申请日：1996-05-17
申请人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
发明人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
IPC分类号： G06F15/78 , G06F13/12
CPC分类号： G06F15/7857 , G06F15/7846 , G06F15/7864
摘要： A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache, provides increased performance over current computer architectures. The multimedia engine includes at least one DSP engines which couple through at least one I/O channels to I/O ports. Obtaining multimedia commands and data from main memory and/or the real-time data cache, the multimedia engine performs a number of multimedia operations including audio and video functions. A CPU, coupled through a chip set logic or bridge logic to the main memory, generates multimedia commands and data. The CPU groups multimedia commands and data into separate command and data elements, and writes the command and data elements to a multimedia address space in main memory. The CPU also writes element structure information to the multimedia address space. The element structure information includes location information used to retrieve multimedia commands and data from main memory. The real-time data cache allows multimedia data from an external source to be stored in a location other than main memory, and allows this multimedia data to be shared by the CPU and the multimedia engine. The real-time data cache may also store multimedia commands and data for use by the multimedia engine.
摘要翻译：介绍了一种针对实时多媒体应用优化的计算机系统和方法。计算机系统，包括直接耦合到实时数据缓存的专用多媒体引擎，提供了超过当前计算机体系结构的性能。多媒体引擎包括至少一个通过至少一个I / O通道耦合到I / O端口的DSP引擎。从主存储器和/或实时数据高速缓存获取多媒体命令和数据，多媒体引擎执行包括音频和视频功能的多种多媒体操作。通过芯片组逻辑或桥接逻辑耦合到主存储器的CPU产生多媒体命令和数据。 CPU将多媒体命令和数据分组到单独的命令和数据元素中，并将命令和数据元素写入主存储器中的多媒体地址空间。 CPU还将元素结构信息写入多媒体地址空间。元素结构信息包括用于从主存储器检索多媒体命令和数据的位置信息。实时数据高速缓存允许来自外部源的多媒体数据被存储在主存储器以外的位置，并允许该多媒体数据由CPU和多媒体引擎共享。实时数据高速缓存还可以存储由多媒体引擎使用的多媒体命令和数据。

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