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91. 发明申请

US20010052047A1 Integrated circuit for modem 审中-公开
标题翻译：调制解调器集成电路
公开(公告)号：US20010052047A1
公开(公告)日：2001-12-13
申请号：US09873649
申请日：2001-06-04
申请人： NEC Corporation
发明人： Mitsuhiro Ono
IPC分类号： G06F012/08
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0851 , G06F12/1045 , G06F15/7846 , G06F15/7857
摘要： To reduce the circuit area and cost of the integrated circuit for modem. The RAM controller 5 performs such a control that the instructions are prefetched from the external instruction ROM to the instruction RAM 2 on a bank basis and the instruction RAM 2 is caused to operate as a cache memory for the external instruction ROM and the CPU and the hardware unit 1 are caused to the time-divisionally share part of banks of the instruction RAM 2.
摘要翻译：降低调制解调器集成电路的电路面积和成本。 RAM控制器5执行这样的控制，使得指令从外部指令ROM预取到基于存储体的指令RAM2，并且使指令RAM2作为用于外部指令ROM和CPU的高速缓存存储器和硬件单元1被分时地共享指令RAM 2的一部分。

92. 发明授权

US06282631B1 Programmable RISC-DSP architecture 有权
标题翻译：可编程RISC-DSP架构
公开(公告)号：US06282631B1
公开(公告)日：2001-08-28
申请号：US09220158
申请日：1998-12-23
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： G06F1500
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/34 , G06F9/345 , G06F9/3455 , G06F9/3879 , G06F15/7857
摘要： The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.
摘要翻译：本发明提供一种能够实现高效数字信号处理的音频信号处理器及其操作方法。快速乘法累加（MAC）和矢量处理能力在RISC架构中实现，为数字信号处理系统的高速能力提供了RISC处理器的速度和效率。

93. 发明授权

US06230235B1 Address lookup DRAM aging 有权
标题翻译：地址查找DRAM老化
公开(公告)号：US06230235B1
公开(公告)日：2001-05-08
申请号：US09163074
申请日：1998-09-29
申请人： Hsuehchung Shelton Lu , David Keene
发明人： Hsuehchung Shelton Lu , David Keene
IPC分类号： G06F1200
CPC分类号： G06F9/5016 , G06F12/0215 , G06F15/7857 , G11C11/406
摘要： Systems and methods are described for network address lookup entry aging in a DRAM memory. A method of DRAM data aging includes: refreshing a row of memory cells in an array of DRAM memory cells. The refreshing periodically includes aging all entries that are stored in the row of memory cells. The systems and methods provide advantages in that an existing operation is used for an additional function. In addition, the aging can be implemented with closely coupled logic using the sense amplifiers.
摘要翻译：描述了DRAM存储器中的网络地址查找条目老化的系统和方法。 DRAM数据老化的方法包括：刷新DRAM存储器单元阵列中的一行存储器单元。刷新周期性地包括老化存储在存储单元行中的所有条目。这些系统和方法提供了一个优点，即现有操作用于附加功能。此外，可以使用感测放大器使用紧密耦合的逻辑来实现老化。

94. 发明授权

US06175881B1 Microcontroller having a memory, a dedicated multitask memory, and switching circuit for selectively connecting the multitask memory to the internal or external bus 失效
标题翻译：具有存储器的微控制器，专用多任务存储器和用于选择性地将多任务存储器连接到内部或外部总线的切换电路
公开(公告)号：US06175881B1
公开(公告)日：2001-01-16
申请号：US09038836
申请日：1998-03-12
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F1310
CPC分类号： G06F15/7857
摘要： A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.
摘要翻译：一种微控制器，包括CPU1用于执行算术运算的第一存储器2; 用于在CPU1的运算处理期间存储从外部设备30传送的数据的多任务处理的第二存储器3; 总线开关4和5用于切换CPU1和外部设备30的数据总线的连接; 以及地址供应部分7，其连接到外部设备30的地址总线，同时第二存储器3连接到外部设备30的数据总线，并且产生用于存储来自外部设备的数据的地址信号，其中该微控制器可以执行多任务处理而不采用昂贵的设备，例如双端口RAM。

95. 发明授权

US6138136A Signal processor 有权
标题翻译：信号处理器
公开(公告)号：US6138136A
公开(公告)日：2000-10-24
申请号：US11673
申请日：1998-10-23
申请人： Harald Bauer , Dietmar Lorenz , Peter Meyer , Roberto Woudsma
发明人： Harald Bauer , Dietmar Lorenz , Peter Meyer , Roberto Woudsma
IPC分类号： G06F17/10 , G06F15/78 , G06F7/38
CPC分类号： G06F15/7857
摘要： A signal processor includes at least one data source (3), a plurality of input registers (11, 12, 13, 14, . . . ) whose inputs are coupled to the data source by data buses (9, 10), a plurality of multipliers (19, 20; 71, 72 . . . ) for multiplying data buffered in the input registers, and a processing arrangement spread over a plurality of data processor branches (4-0, 4-1, . . . , 4-N) for processing products (p0, p1, . . . ), generated by the multipliers by arithmetic and/or logic operations. For achieving enhanced flexibility of the signal processor and increasing the number of possible applications, multiplexers (15, 16, 17, 18; 70) are provided which are used for coupling the multipliers to a respective part of the input registers in dependence on control signals (I, II, III, IV). Such a signal processor is preferably used in mobile radio technology. Further fields of application are, for example, audio, video, medical and automotive technology, ISDN systems, and digital radio.
摘要翻译： PCT No.PCT / IB97 / 00760 Sec。 371 1998年10月23日第 102（e）日期1998年10月23日PCT提交1997年6月23日PCT公布。公开号WO97 / 50030 日期1997年12月31日信号处理器包括至少一个数据源（3），多个输入寄存器（11,12,13,14，...，...），其输入通过数据总线（9， 10），用于乘以在输入寄存器中缓冲的数据的多个乘法器（19,20; 71,72 ...）和分布在多个数据处理器分支（4-0，4-1，...）上的处理装置。 ...，4-N），用于通过算术和/或逻辑运算来生成由乘法器产生的乘积（p0，p1，...）。为了实现增强的信号处理器的灵活性并增加可能的应用的数量，提供多路复用器（15,16,17,18; 70），其用于根据控制信号将乘法器耦合到输入寄存器的相应部分（I，II，III，IV）。这样的信号处理器优选地用于移动无线电技术中。其他应用领域是例如音频，视频，医疗和汽车技术，ISDN系统和数字无线电。

96. 发明授权

US6104658A Distributed DRAM refreshing 有权
标题翻译：分布式DRAM刷新
公开(公告)号：US6104658A
公开(公告)日：2000-08-15
申请号：US162943
申请日：1998-09-29
申请人： Hsuehchung Shelton Lu
发明人： Hsuehchung Shelton Lu
IPC分类号： G06F9/50 , G06F12/02 , G06F15/78 , G11C11/406 , G11C7/00 , G11C8/00
CPC分类号： G06F12/0215 , G06F15/7857 , G06F9/5016 , G11C11/406
摘要： Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.
摘要翻译：描述了用于分布式DRAM刷新的系统和方法。分布式DRAM刷新的方法包括：用第一行读出放大器刷新DRAM存储单元的第一阵列中的第一行存储单元; 然后用第二行读出放大器刷新DRAM存储单元的第二阵列中的第二行存储单元。这些系统和方法提供了能够降低功率瞬变（噪声）的大小的优点。此外，当阵列被布置在多个子组中时，可以提高性能。

97. 发明授权

US5898892A Computer system with a data cache for providing real-time multimedia data to a multimedia engine 失效
标题翻译：具有用于向多媒体引擎提供实时多媒体数据的数据高速缓存的计算机系统
公开(公告)号：US5898892A
公开(公告)日：1999-04-27
申请号：US650941
申请日：1996-05-17
申请人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
发明人： Dale E. Gulick , Andy Lambrecht , Mike Webb , Larry Hewitt , Brian Barnes
IPC分类号： G06F15/78 , G06F13/12
CPC分类号： G06F15/7857 , G06F15/7846 , G06F15/7864
摘要： A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache, provides increased performance over current computer architectures. The multimedia engine includes at least one DSP engines which couple through at least one I/O channels to I/O ports. Obtaining multimedia commands and data from main memory and/or the real-time data cache, the multimedia engine performs a number of multimedia operations including audio and video functions. A CPU, coupled through a chip set logic or bridge logic to the main memory, generates multimedia commands and data. The CPU groups multimedia commands and data into separate command and data elements, and writes the command and data elements to a multimedia address space in main memory. The CPU also writes element structure information to the multimedia address space. The element structure information includes location information used to retrieve multimedia commands and data from main memory. The real-time data cache allows multimedia data from an external source to be stored in a location other than main memory, and allows this multimedia data to be shared by the CPU and the multimedia engine. The real-time data cache may also store multimedia commands and data for use by the multimedia engine.
摘要翻译：介绍了一种针对实时多媒体应用优化的计算机系统和方法。计算机系统，包括直接耦合到实时数据缓存的专用多媒体引擎，提供了超过当前计算机体系结构的性能。多媒体引擎包括至少一个通过至少一个I / O通道耦合到I / O端口的DSP引擎。从主存储器和/或实时数据高速缓存获取多媒体命令和数据，多媒体引擎执行包括音频和视频功能的多种多媒体操作。通过芯片组逻辑或桥接逻辑耦合到主存储器的CPU产生多媒体命令和数据。 CPU将多媒体命令和数据分组到单独的命令和数据元素中，并将命令和数据元素写入主存储器中的多媒体地址空间。 CPU还将元素结构信息写入多媒体地址空间。元素结构信息包括用于从主存储器检索多媒体命令和数据的位置信息。实时数据高速缓存允许来自外部源的多媒体数据被存储在主存储器以外的位置，并允许该多媒体数据由CPU和多媒体引擎共享。实时数据高速缓存还可以存储由多媒体引擎使用的多媒体命令和数据。

98. 发明授权

US5535288A System and method for cross correlation with application to video motion vector estimator 失效
标题翻译：与应用于视频运动矢量估计的互相关的系统和方法
公开(公告)号：US5535288A
公开(公告)日：1996-07-09
申请号：US388181
申请日：1995-02-10
申请人： Chih-Kang Chen , Jerome F. Duluk, Jr.
发明人： Chih-Kang Chen , Jerome F. Duluk, Jr.
IPC分类号： G06F15/78 , G06F17/15 , G06T7/20 , H04N5/14 , H04N7/26 , H04N7/50
CPC分类号： G06T7/202 , G06F15/7857 , G06F17/15 , G06F17/153 , H04N19/42 , H04N19/43 , H04N19/51 , H04N19/61 , H04N5/145 , G06T2207/10016 , G06T2207/20056
摘要： Method and apparatus for computing cross-correlations with application to image processing and video motion estimation, particularly in video compression applications, are described. Two-dimensional Fourier transform convolution techniques form a basis for novel techniques for performing two simultaneous two-dimensional cross correlations. The size of the input data blocks for the transformations are arbitrary. Apparatus for efficiently performing real-time cross correlations, including cross-correlations using Short Length Transforms (SLTs), using cascaded stages, multi-port memories, and multiple arithmetic units are also described. In video motion vector estimator application, data blocks within a current video frame are selected and converted to form a two-dimensional matrix of complex data. The complex matrix is transformed to the frequency domain to form the frequency domain representations of the selected data blocks. A set of search blocks within the previous video frame having a one-to-one correspondence with the selected data blocks, is then selected, converted into a complex data matrix, and transformed to the frequency domain to form the frequency domain representations of the selected search blocks. Once in the frequency domain, the sets of data corresponding to the data blocks and the search blocks are multiplied together and the product is inverse transformed to return to the spatial domain. The data then passes through an adjustment process to form the cross-correlations between the pairs of data blocks and search blocks.
摘要翻译：描述了用于计算与应用于图像处理和视频运动估计的交叉相关性的方法和装置，特别是在视频压缩应用中。二维傅立叶变换卷积技术形成了用于执行两个同时二维互相关的新技术的基础。转换的输入数据块的大小是任意的。还描述了用于有效执行实时互相关的装置，包括使用短距离变换（SLT）的互相关，使用级联级，多端口存储器和多个运算单元。在视频运动矢量估计器应用中，选择并转换当前视频帧内的数据块以形成复数数据的二维矩阵。将复数矩阵变换到频域以形成所选数据块的频域表示。然后选择与所选数据块具有一一对应关系的先前视频帧内的一组搜索块，将其转换为复数数据矩阵，并变换到频域以形成所选择的数据块的频域表示搜索块。一旦在频域中，与数据块和搜索块相对应的数据集合被相乘并且乘积被逆变换以返回到空间域。数据然后通过调整过程以形成数据块和搜索块之间的互相关。

99. 发明授权

US5333261A Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers 失效
标题翻译：具有分别在像素位置寄存器的X和Y坐标上操作的指令的图形处理装置
公开(公告)号：US5333261A
公开(公告)日：1994-07-26
申请号：US59006
申请日：1993-05-07
申请人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
IPC分类号： G06F9/345 , G06F9/38 , G06F15/78 , G06T1/20 , G06F15/20
CPC分类号： G06F9/345 , G06F15/7857 , G06F9/3885 , G06T1/20
摘要： The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.
摘要翻译：本发明的图形处理装置利用寄存器文件的各个寄存器来存储像素的X和Y坐标。这些X和Y坐标虽然形成单个数据字，但是可以通过例如具有指定Y坐标的最高有效位和指定Y坐标的最低有效位来分离。图形处理装置支持提供对这些X和Y坐标的单独且独立的数据操纵的指令。这些X Y坐标操作指令可以为两个数据字提供单独的X Y算术运算，分别进行X和Y比较运算，单独的X和Y数据移动操作以及X Y地址格式与线性地址格式之间的转换。该技术对于使用位映射图形的可视显示系统中的X Y地址坐标的操纵非常有用。

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