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1. 发明授权

US06175881B1 Microcontroller having a memory, a dedicated multitask memory, and switching circuit for selectively connecting the multitask memory to the internal or external bus 失效
标题翻译：具有存储器的微控制器，专用多任务存储器和用于选择性地将多任务存储器连接到内部或外部总线的切换电路
公开(公告)号：US06175881B1
公开(公告)日：2001-01-16
申请号：US09038836
申请日：1998-03-12
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F1310
CPC分类号： G06F15/7857
摘要： A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.
摘要翻译：一种微控制器，包括CPU1用于执行算术运算的第一存储器2; 用于在CPU1的运算处理期间存储从外部设备30传送的数据的多任务处理的第二存储器3; 总线开关4和5用于切换CPU1和外部设备30的数据总线的连接; 以及地址供应部分7，其连接到外部设备30的地址总线，同时第二存储器3连接到外部设备30的数据总线，并且产生用于存储来自外部设备的数据的地址信号，其中该微控制器可以执行多任务处理而不采用昂贵的设备，例如双端口RAM。

2. 发明授权

US5339271A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5339271A
公开(公告)日：1994-08-16
申请号：US846205
申请日：1992-03-04
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G11C17/00 , G11C8/08 , G11C16/04 , G11C16/10 , G11C16/34 , G11C29/00 , G11C29/12 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50004 , G11C16/0441 , G11C16/10 , G11C16/34 , G11C29/50 , G11C8/08 , G06F2201/81 , G11C16/04
摘要： A semiconductor memory circuit includes memory cells each having two storage semiconductor elements. One of these semiconductor elements is made inoperative in response to a first or a second operation control signal. This makes it possible to check the margin of a threshold voltage of the other storage semiconductor element at the time when writing, erasing and reading operations with respect thereto are being performed.
摘要翻译：半导体存储电路包括具有两个存储半导体元件的存储单元。响应于第一或第二操作控制信号使这些半导体元件中的一个不工作。这使得可以在执行与之相关的写入，擦除和读取操作时检查另一个存储半导体元件的阈值电压的余量。

3. 发明授权

US5119330A Nonvolatile memory system for multiple value storing 失效
标题翻译：用于多值存储的非易失性存储系统
公开(公告)号：US5119330A
公开(公告)日：1992-06-02
申请号：US498685
申请日：1990-03-26
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C11/5642 , G11C11/5692
摘要： A nonvolatile memory system for one of a multiple of values includes a memory cell having an input terminal, an output terminal, and a control terminal. The memory cell, which may be an EEPROM, stores nonvolatile electric charge, and establishes a voltage threshold between the input terminal and the output terminal which influences a current therebetween, the threshold having a level which is dependent upon the amount of the electric charge stored by the storing means. A writing circuit is connected to the input terminal and is responsive to an input data signal having a value selected from among at least three values for applying electric charge, in an amount corresponding to the value of the selected data signal, to the input terminal for storage in the memory cell. A reading circuit is provided to measure the value of the voltage threshold between the input and output terminals and to output a data signal having a value which corresponds to the measured value of the threshold voltage. In its preferred embodiments, the system is an electrically erasable programmable read only memory system which can store multiple values in a single memory cell.

4. 发明授权

US5062075A Microcomputer having security memory using test and destruction routines 失效
标题翻译：具有使用测试和销毁程序的安全存储器的微型计算机
公开(公告)号：US5062075A
公开(公告)日：1991-10-29
申请号：US449050
申请日：1989-12-14
申请人： Tomoaki Yoshida , Kouji Tanagawa
发明人： Tomoaki Yoshida , Kouji Tanagawa
IPC分类号： G06F11/00 , G06F11/22 , G06F12/14 , G06F21/22
CPC分类号： G06F12/1433
摘要： In a single-chip microcomputer having a first memory storing security data and a second memory for storing a test program. The test program includes test routines and a destruction routine to be executed prior to the test routines. The destruction routine destroys the security data in the first memory.
摘要翻译：在具有存储安全数据的第一存储器和用于存储测试程序的第二存储器的单片微计算机中。测试程序包括在测试程序之前执行的测试例程和销毁程序。破坏程序会破坏第一个内存中的安全数据。

5. 发明授权

US4875156A Computer having a protection device to selectively block incorrect control signals 失效
标题翻译：计算机具有保护装置以选择性地阻止不正确的控制信号
公开(公告)号：US4875156A
公开(公告)日：1989-10-17
申请号：US22062
申请日：1987-03-03
申请人： Kouji Tanagawa , Tomoaki Yoshida
发明人： Kouji Tanagawa , Tomoaki Yoshida
IPC分类号： G06F11/28 , G06F11/00 , G06F12/14
CPC分类号： G06F12/1441 , G06F11/00
摘要： In a computer having a program including a first type of instruction and a second type of instruction, a program memory has a first area for storing the first type of instruction and a second area for storing the second type of instruction. An address code is supplied from a program counter to the program memory, which thereby produces an instruction code stored at the addressed memory location. A control unit is responsive to the instruction code from the program memory for producing a control signal for controlling the operation of the computer. A protection circuit is provided for preventing execution of the first type of instruction when the address code output from the program counter does not designate any memory location in the first area.
摘要翻译：在具有包括第一类型指令和第二类型指令的程序的计算机中，程序存储器具有用于存储第一类型指令的第一区域和用于存储第二类型指令的第二区域。从程序计数器向程序存储器提供地址代码，从而产生存储在所寻址的存储器位置的指令代码。控制单元响应于来自程序存储器的指令代码，用于产生用于控制计算机的操作的控制信号。当从程序计数器输出的地址代码未指定第一区域中的任何存储器位置时，提供保护电路以防止执行第一类型的指令。

6. 发明授权

US5101483A Instruction decoder simplification by reuse of bits to produce the same control states for different instructions 失效
标题翻译：指令解码器通过重复使用生成相同控制状态的不同指令进行简化
公开(公告)号：US5101483A
公开(公告)日：1992-03-31
申请号：US415275
申请日：1989-09-22
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G01R31/3185 , G06F9/30 , G06F9/318 , G06F11/273
CPC分类号： G06F9/30156 , G01R31/318516 , G06F9/30145 , G06F11/2736
摘要： A microcomputer having a memory which stores coded instructions. An instruction register coupled to the memory is used for temporarily storing instructions one byte at a time. A programmable logic array is coupled to the register and has a decoder which decodes the bytes of the instruction in the register to provide control signals, the bytes of each instruction temporarily stored in the register producing control signals during each of at least first and second successive machine cycles. Where it is desired that control signals produced during the second machine cycle with a second instruction stored in the register includes all of the control signals produced during a second machine cycle with a first instruction stored in the register this is accomplished with a reduced number of decode lines in the array by providing that (1) a second byte of the first instruction has the same code as that of a first byte of the first instruction so that a single decode line can be used for decoding the first byte of the first instruction and the second byte of the second instruction, and (2) the array includes circuit elements which load the second byte of the second instruction from the memory into the register to be decoded by the decoder during the second machine cycle after a first byte of the second instruction has been loaded into the register and decoded by the decoder.
摘要翻译： PCT No.PCT / JP89 / 00065 Sec。 371日期：1989年9月22日 102（e）1989年9月22日PCT PCT 1月25日PCT公布。公开号WO89 / 07297 日期：1989年8月10日。一种具有存储编码指令的存储器的微型计算机。耦合到存储器的指令寄存器用于一次一个字节地临时存储指令。可编程逻辑阵列耦合到寄存器，并且具有解码器，其解码寄存器中的指令的字节以提供控制信号，临时存储在寄存器中的每个指令的字节在至少第一和第二连续的每一个期间产生控制信号机器周期。在期望在第二机器周期期间产生的控制信号中存储在寄存器中的第二指令包括在第二机器周期期间产生的所有控制信号，其中存储在寄存器中的第一指令是用减少数量的解码通过提供（1）第一指令的第二字节具有与第一指令的第一字节相同的代码，使得单个解码线可用于对第一指令的第一个字节进行解码，并且第二指令的第二字节，以及（2）阵列包括电路元件，其将第二指令的第二字节从存储器加载到由第二机器周期内的解码器解码的寄存器中，第二个字节在第二个指令的第一个字节之后指令已经被加载到寄存器中并被解码器解码。

7. 发明授权

US5068783A Microcomputer having a built-in PROM for storing an optional program 失效
标题翻译：具有存储可选程序的内置PROM的微型计算机
公开(公告)号：US5068783A
公开(公告)日：1991-11-26
申请号：US915804
申请日：1986-10-06
申请人： Kouji Tanagawa , Tomoaki Yoshida
发明人： Kouji Tanagawa , Tomoaki Yoshida
IPC分类号： G06F11/22 , G06F11/267 , G06F15/78
CPC分类号： G06F11/2236
摘要： A microcomputer selectively operable in a first mode or a second mode comprises a first read-only memory for storing a first program to be executed in the first mode, a second, programmable read-only memory for storing a second program to be executed in the second mode, an input circuit for inputting the second program to be written in the second read-only memory, an execution circuit for executing the first program or the second program, and a mode control circuit responsive to a mode selection signal for enabling execution of the first program when the mode selection signal designates the first mode and for enabling writing and execution of the second program when the mode selection signal designates the second mode.
摘要翻译：选择性地以第一模式或第二模式操作的微计算机包括用于存储要在第一模式中执行的第一程序的第一只读存储器，用于存储要在第一模式或第二模式中执行的第二程序的第二可编程只读存储器第二模式，用于输入要写入第二只读存储器的第二程序的输入电路，用于执行第一程序或第二程序的执行电路，以及响应于模式选择信号的模式控制电路，当模式选择信号指定第一模式时，第一程序和用于当模式选择信号指定第二模式时能够写入和执行第二程序。

8. 发明授权

US4866608A Microprocessor with improved execution of instructions 失效
标题翻译：微处理器改进执行指令
公开(公告)号：US4866608A
公开(公告)日：1989-09-12
申请号：US926539
申请日：1986-11-04
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F15/78 , G06F9/30 , G06F9/318 , G06F9/34
CPC分类号： G06F9/30181 , G06F9/34 , G06F9/3824
摘要： In a computer, an address value is transferred to data pointer and a data is transfered from a memory location of a data memory being designated by the address value in the data pointer to a temporary register, the transfer of the address value and the transfer of the data being conducted within a first instruction cycle. In a second instruction cycle immediately following the first instruction cycle, an operation is performed by an ALU on data in an accumulater and the temporary register, and the result of operation is transferred to the accumulator and to the memory location of the data memory being designated by the data pointer.
摘要翻译：在计算机中，将地址值传送到数据指针，并将数据从数据指针中的地址值指定的数据存储器的存储器位置传送到临时寄存器，地址值的传送和数据在第一指令周期内进行。在第一指令周期之后的第二指令周期中，由ALU对累加器和临时寄存器中的数据执行操作，并且操作结果被传送到指定的数据存储器的存储单元由数据指针。

9. 发明授权

US5337280A EEPROM circuit 失效
标题翻译： EEPROM电路
公开(公告)号：US5337280A
公开(公告)日：1994-08-09
申请号：US766564
申请日：1991-09-27
申请人： Kouji Tanagawa , Kazuhiko Miyazaki
发明人： Kouji Tanagawa , Kazuhiko Miyazaki
IPC分类号： G11C16/04 , G11C16/10 , G11C16/14 , G11C16/26 , G11C7/00
CPC分类号： G11C16/10 , G11C16/0441 , G11C16/14 , G11C16/26
摘要： An EEPROM circuit has two memory transistors in a memory cell of an array. Stored data is read out to a reading circuit via a first and second complementary bit lines. A writing circuit provides voltage to the cell so that the first memory transistor writes data and the second memory transistor erases data. An erasing circuit does the converse, i.e. provides voltage to the cell so that the first memory transistor erases data and the second memory transistor writes data.
摘要翻译： EEPROM电路在阵列的存储单元中具有两个存储晶体管。存储的数据通过第一和第二互补位线读出到读取电路。写入电路向单元提供电压，使得第一存储器晶体管写入数据，并且第二存储器晶体管擦除数据。擦除电路相反，即向单元提供电压，使得第一存储器晶体管擦除数据，并且第二存储器晶体管写入数据。

10. 发明授权

US5088027A Single-chip microcomputer 失效
标题翻译：单芯片微型计算机
公开(公告)号：US5088027A
公开(公告)日：1992-02-11
申请号：US572545
申请日：1990-08-27
申请人： Kouji Tanagawa , Tomoaki Yoshida
发明人： Kouji Tanagawa , Tomoaki Yoshida
IPC分类号： G06F11/22 , G06F11/34 , G06F11/36 , G06F15/78
CPC分类号： G06F11/3648 , G06F11/3466 , G06F15/786 , G06F11/348
摘要： In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through the internal bus and produces control signals for controlling the operations of the circuit elements, the data written in each of the circuit elements is transmitted to the internal bus during execution of any one of instructions involving transfer of data into the circuit element, and output terminals are provided for outputting part of the control signals from the control circuit and part of the output signals from the circuit elements through the internal bus, the control signals including write control signals for writing data in the circuit elements.

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