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    • 1. 发明授权
    • Microcontroller having a memory, a dedicated multitask memory, and switching circuit for selectively connecting the multitask memory to the internal or external bus
    • 具有存储器的微控制器,专用多任务存储器和用于选择性地将多任务存储器连接到内部或外部总线的切换电路
    • US06175881B1
    • 2001-01-16
    • US09038836
    • 1998-03-12
    • Kouji Tanagawa
    • Kouji Tanagawa
    • G06F1310
    • G06F15/7857
    • A microcontroller comprising a first memory 2 used by a CPU1 to perform arithmetic operations; a second memory 3 for a multitask process for storing data transferred from an external device 30 during the arithmetic process of CPU1; bus switches 4 and 5 for switching over the connection of data buses of CPU1 and the external device 30; and an address supply portion 7, which is connected to the address bus of the external device 30 while the second memory 3 is connected to the data bus of the external device 30, and which generates address signals by which to store data from the external device, wherein this microcontroller can perform a multitask process without adopting an expensive device such as a dual port RAM.
    • 一种微控制器,包括CPU1用于执行算术运算的第一存储器2; 用于在CPU1的运算处理期间存储从外部设备30传送的数据的多任务处理的第二存储器3; 总线开关4和5用于切换CPU1和外部设备30的数据总线的连接; 以及地址供应部分7,其连接到外部设备30的地址总线,同时第二存储器3连接到外部设备30的数据总线,并且产生用于存储来自外部设备的数据的地址信号 ,其中该微控制器可以执行多任务处理而不采用昂贵的设备,例如双端口RAM。
    • 5. 发明授权
    • Computer having a protection device to selectively block incorrect
control signals
    • 计算机具有保护装置以选择性地阻止不正确的控制信号
    • US4875156A
    • 1989-10-17
    • US22062
    • 1987-03-03
    • Kouji TanagawaTomoaki Yoshida
    • Kouji TanagawaTomoaki Yoshida
    • G06F11/28G06F11/00G06F12/14
    • G06F12/1441G06F11/00
    • In a computer having a program including a first type of instruction and a second type of instruction, a program memory has a first area for storing the first type of instruction and a second area for storing the second type of instruction. An address code is supplied from a program counter to the program memory, which thereby produces an instruction code stored at the addressed memory location. A control unit is responsive to the instruction code from the program memory for producing a control signal for controlling the operation of the computer. A protection circuit is provided for preventing execution of the first type of instruction when the address code output from the program counter does not designate any memory location in the first area.
    • 在具有包括第一类型指令和第二类型指令的程序的计算机中,程序存储器具有用于存储第一类型指令的第一区域和用于存储第二类型指令的第二区域。 从程序计数器向程序存储器提供地址代码,从而产生存储在所寻址的存储器位置的指令代码。 控制单元响应于来自程序存储器的指令代码,用于产生用于控制计算机的操作的控制信号。 当从程序计数器输出的地址代码未指定第一区域中的任何存储器位置时,提供保护电路以防止执行第一类型的指令。
    • 6. 发明授权
    • Instruction decoder simplification by reuse of bits to produce the same
control states for different instructions
    • 指令解码器通过重复使用生成相同控制状态的不同指令进行简化
    • US5101483A
    • 1992-03-31
    • US415275
    • 1989-09-22
    • Kouji Tanagawa
    • Kouji Tanagawa
    • G01R31/3185G06F9/30G06F9/318G06F11/273
    • G06F9/30156G01R31/318516G06F9/30145G06F11/2736
    • A microcomputer having a memory which stores coded instructions. An instruction register coupled to the memory is used for temporarily storing instructions one byte at a time. A programmable logic array is coupled to the register and has a decoder which decodes the bytes of the instruction in the register to provide control signals, the bytes of each instruction temporarily stored in the register producing control signals during each of at least first and second successive machine cycles. Where it is desired that control signals produced during the second machine cycle with a second instruction stored in the register includes all of the control signals produced during a second machine cycle with a first instruction stored in the register this is accomplished with a reduced number of decode lines in the array by providing that (1) a second byte of the first instruction has the same code as that of a first byte of the first instruction so that a single decode line can be used for decoding the first byte of the first instruction and the second byte of the second instruction, and (2) the array includes circuit elements which load the second byte of the second instruction from the memory into the register to be decoded by the decoder during the second machine cycle after a first byte of the second instruction has been loaded into the register and decoded by the decoder.
    • PCT No.PCT / JP89 / 00065 Sec。 371日期:1989年9月22日 102(e)1989年9月22日PCT PCT 1月25日PCT公布。 公开号WO89 / 07297 日期:1989年8月10日。一种具有存储编码指令的存储器的微型计算机。 耦合到存储器的指令寄存器用于一次一个字节地临时存储指令。 可编程逻辑阵列耦合到寄存器,并且具有解码器,其解码寄存器中的指令的字节以提供控制信号,临时存储在寄存器中的每个指令的字节在至少第一和第二连续的每一个期间产生控制信号 机器周期。 在期望在第二机器周期期间产生的控制信号中存储在寄存器中的第二指令包括在第二机器周期期间产生的所有控制信号,其中存储在寄存器中的第一指令是用减少数量的解码 通过提供(1)第一指令的第二字节具有与第一指令的第一字节相同的代码,使得单个解码线可用于对第一指令的第一个字节进行解码,并且 第二指令的第二字节,以及(2)阵列包括电路元件,其将第二指令的第二字节从存储器加载到由第二机器周期内的解码器解码的寄存器中,第二个字节在第二个指令的第一个字节之后 指令已经被加载到寄存器中并被解码器解码。
    • 7. 发明授权
    • Microcomputer having a built-in PROM for storing an optional program
    • 具有存储可选程序的内置PROM的微型计算机
    • US5068783A
    • 1991-11-26
    • US915804
    • 1986-10-06
    • Kouji TanagawaTomoaki Yoshida
    • Kouji TanagawaTomoaki Yoshida
    • G06F11/22G06F11/267G06F15/78
    • G06F11/2236
    • A microcomputer selectively operable in a first mode or a second mode comprises a first read-only memory for storing a first program to be executed in the first mode, a second, programmable read-only memory for storing a second program to be executed in the second mode, an input circuit for inputting the second program to be written in the second read-only memory, an execution circuit for executing the first program or the second program, and a mode control circuit responsive to a mode selection signal for enabling execution of the first program when the mode selection signal designates the first mode and for enabling writing and execution of the second program when the mode selection signal designates the second mode.
    • 选择性地以第一模式或第二模式操作的微计算机包括用于存储要在第一模式中执行的第一程序的第一只读存储器,用于存储要在第一模式或第二模式中执行的第二程序的第二可编程只读存储器 第二模式,用于输入要写入第二只读存储器的第二程序的输入电路,用于执行第一程序或第二程序的执行电路,以及响应于模式选择信号的模式控制电路, 当模式选择信号指定第一模式时,第一程序和用于当模式选择信号指定第二模式时能够写入和执行第二程序。