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91. 发明申请

US20130332665A1 MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE 有权
标题翻译：具有银行冲突解决（BCR）模块的记忆，包括缓存
公开(公告)号：US20130332665A1
公开(公告)日：2013-12-12
申请号：US13841025
申请日：2013-03-15
申请人： MOSYS, INC.
发明人： Dipak Sikdar , Michael J. Miller , Jay Patel
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F12/0802 , G06F2212/304 , G11C7/1039 , G11C8/12 , G11C8/18 , G11C11/417 , G11C2207/2209 , G11C2207/2245
摘要： A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
摘要翻译：存储器件包括存储器单元块和高速缓存。存储器单元块不是具有多个端口的随机存取存储器。存储器单元块被分割成仅具有单个端口的子单元。高速缓存耦合到适于处理对存储器单元的相同子单元的多个访问的存储器单元块而不产生冲突，使得存储器看起来是对所述多个访问的随机存取存储器。还提供了一种操作存储器的方法，以及具有包含缓存的存储体冲突解决（BCR）模块的存储器。

92. 发明申请

US20130313723A1 SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS 有权
标题翻译：带有STAGGERED TX和TX数据线的半导体芯片布局
公开(公告)号：US20130313723A1
公开(公告)日：2013-11-28
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/538
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

93. 发明授权

US08587046B2 System with logic and embedded MIM capacitor 有权
标题翻译：具有逻辑和嵌入式MIM电容的系统
公开(公告)号：US08587046B2
公开(公告)日：2013-11-19
申请号：US13191423
申请日：2011-07-26
申请人： Jeong Y Choi
发明人： Jeong Y Choi
IPC分类号： H01L27/108 , H01L21/8242 , G11C11/24
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/91
摘要： An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the memory region than in the logic region.
摘要翻译：嵌入式存储器系统包括与逻辑晶体管阵列相同的衬底上的随机存取存储器（RAM）单元阵列。每个RAM单元包括存取晶体管和电容器结构。通过在电介质层中形成金属 - 绝缘体 - 金属电容器来制造电容器结构。嵌入式RAM系统在存储器区域中比在逻辑区域中包括更少的金属层。

94. 发明申请

US20130173970A1 MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR 有权
标题翻译：具有背景技术的存储器件内置自检和背景技术自我修复
公开(公告)号：US20130173970A1
公开(公告)日：2013-07-04
申请号：US13732783
申请日：2013-01-02
申请人： Bendik Kleveland , Dipak K. Sikdar , Rajesh Chopra , Jay Patel
发明人： Bendik Kleveland , Dipak K. Sikdar , Rajesh Chopra , Jay Patel
IPC分类号： G11C29/44
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
摘要翻译：具有背景内置自检（BBIST）的存储器件包括多个存储器块; 一个用于临时从多个存储块中的一个存储器块中的一个卸载数据的存储器缓冲器; 以及存储器块应力控制器，用于当数据被暂时地卸载到存储器缓冲器上时，控制施加到存储器块之一的压力测试。压力测试测试多个存储器块中的一个存储器块中的错误。

95. 发明申请

US20130154698A1 DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT 有权
标题翻译：延迟锁定环路进行相位调整
公开(公告)号：US20130154698A1
公开(公告)日：2013-06-20
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

96. 发明授权

US08446755B2 Multiple cycle memory write completion 有权
标题翻译：多周期内存写入完成
公开(公告)号：US08446755B2
公开(公告)日：2013-05-21
申请号：US13369253
申请日：2012-02-08
申请人： Richard S. Roy
发明人： Richard S. Roy
IPC分类号： G11C11/24 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1015 , G11C11/406 , G11C11/40618 , G11C2207/229
摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.
摘要翻译：一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

97. 发明授权

US08361863B2 Embedded DRAM with multiple gate oxide thicknesses 有权
标题翻译：具有多个栅极氧化物厚度的嵌入式DRAM
公开(公告)号：US08361863B2
公开(公告)日：2013-01-29
申请号：US12291765
申请日：2008-11-13
申请人： Jeong Y. Choi
发明人： Jeong Y. Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/10894 , H01L27/1085 , H01L27/10861 , H01L27/10873 , H01L29/66181
摘要： A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells.
摘要翻译：一种形成具有多层栅极电介质的嵌入式DRAM单元的方法。将氧化增强掺杂剂选择性地注入到通过第一掩模曝光的区域中的阱区中。热氧化步骤同时产生两个不同器件的场电介质，每个不同的器件具有不同的氧化物厚度。该方法适用于使用较少氧化步骤的四密度DRAM单元。该方法也适用于平面DRAM单元，并且在制造平面DRAM单元期间不需要增加掩模的数量。

98. 发明授权

US08269538B2 Signal alignment system 有权
标题翻译：信号对准系统
公开(公告)号：US08269538B2
公开(公告)日：2012-09-18
申请号：US12768513
申请日：2010-04-27
申请人： Mahmudul Hassan
发明人： Mahmudul Hassan
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/1051 , G11C7/1066 , G11C2207/2254 , H03L7/091
摘要： Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal.
摘要翻译：通过使用多级扫描，本发明能够提高速度并提高信号对准的误差电阻。在本发明的具体实施例中，公开了一种用于目标信号和可调信号的信号对准的方法。使用三个或更多个可调信号的相移版本对目标信号进行采样，以获得一组目标信号状态值。接下来，通过参考该组目标信号状态值，确定目标信号的边缘位于第一相移版本和第二连续移相版本之间。作为响应，选择第一相移版本作为第二扫描的起始点。在第二扫描期间，以相对小的增量步长依次调整第一相移版本的相位，以使相对于目标信号的相位差最小化。

99. 发明授权

US08171234B2 Multi-bank multi-port architecture 有权
标题翻译：多银行多端口架构
公开(公告)号：US08171234B2
公开(公告)日：2012-05-01
申请号：US12404955
申请日：2009-03-16
申请人： Kit Sang Tam
发明人： Kit Sang Tam
IPC分类号： G06F12/00
CPC分类号： G06F13/161
摘要： A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.
摘要翻译：一种包括多个端口的存储器系统和具有多个存储体的存储器核心。在端口处接收到的接入请求被广播到存储体。响应于在不同端口上接收到的访问请求，可以同时访问多个存储器组。存储器控制器向存储器系统提供访问请求，并且确保单个存储器组不被不同端口同时访问。所有访问请求都以相同的延迟进行处理。如果存储体包括必须定期刷新的存储器单元，则存储器控制器还向存储体提供刷新请求。由于可以响应于在不同端口上提供的访问请求而同时访问多个存储体，所以存储体可以以比端口更低的频率工作。

100. 发明申请

US20120025347A1 Method of forming a MIM capacitor 有权
标题翻译：形成MIM电容器的方法
公开(公告)号：US20120025347A1
公开(公告)日：2012-02-02
申请号：US12804855
申请日：2010-07-30
申请人： Jeong Y. Choi
发明人： Jeong Y. Choi
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10882 , H01L27/10888
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, on the same substrate as an array of logic transistors. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The eDRAM system includes fewer metal layers in the logic area than in the memory area
摘要翻译：嵌入式存储器系统包括与逻辑晶体管阵列相同的衬底上的动态随机存取存储器（DRAM）单元阵列。每个DRAM单元包括存取晶体管和电容器结构。通过在电介质层中形成金属 - 绝缘体 - 金属电容器来制造电容器结构。 eDRAM系统在逻辑区域中包含的金属层比内存区域少

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