专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US5854562A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US5854562A
公开(公告)日：1998-12-29
申请号：US842536
申请日：1997-04-15
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

92. 发明授权

US5604417A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5604417A
公开(公告)日：1997-02-18
申请号：US992448
申请日：1992-12-17
申请人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
发明人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
IPC分类号： H01L27/06 , H03K19/013 , H03R19/013
CPC分类号： H01L27/0623 , H03K19/0136
摘要： The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.
摘要翻译：该装置在单个基板上具有多个内部电路，用于接收外部输入信号并将其输出到内部电路的多个输入电路，以及用于接收从内部电路输出并从外部输出信号的多个输出电路，其中至少一个电路包括位于电源端侧的第一NPN双极晶体管的图腾柱输出级和位于地侧的第二NPN双极晶体管; 用于向第一NPN晶体管的基极提供脉冲作用的第一微分电路; 一对用于可控地驱动第二NPN晶体管的串联PMOS晶体管; 以及用于加速输出级晶体管关断的反馈MOS晶体管。电路可以用第二微分电路代替串联连接的一对PMOS晶体管。还可以实现电路的布置，其中图腾柱连接由PNP晶体管，电源端侧和地面或下拉侧的NPN或NMOS晶体管构成。利用这种电路配置，输出信号摆幅最大化，微分电路提供临时饱和以及快速恢复，从而减少传输延迟时间并实现低功耗。该设备可以由采用自举效应以及IIL（I2L）设计方案的电路来实现。

93. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

94. 发明授权

US5377136A Semiconductor integrated circuit device with built-in memory circuit group 失效
标题翻译：具有内置存储电路组的半导体集成电路器件
公开(公告)号：US5377136A
公开(公告)日：1994-12-27
申请号：US076874
申请日：1993-06-15
申请人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
发明人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
IPC分类号： G11C5/06 , G11C8/16
CPC分类号： G11C8/16 , G11C5/063
摘要： A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
摘要翻译：公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

95. 发明授权

US4890017A CMOS-BiCMOS gate circuit 失效
标题翻译： CMOS-BiCMOS门电路
公开(公告)号：US4890017A
公开(公告)日：1989-12-26
申请号：US127184
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

96. 发明授权

US4719373A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4719373A
公开(公告)日：1988-01-12
申请号：US45216
申请日：1987-04-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/60 , H03K3/33
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

97. 发明授权

US4589007A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4589007A
公开(公告)日：1986-05-13
申请号：US529764
申请日：1983-09-06
申请人： Shigeo Kuboki , Mitsuhiro Ikeda , Akihiko Takano , Yoji Nishio , Ikuro Masuda
发明人： Shigeo Kuboki , Mitsuhiro Ikeda , Akihiko Takano , Yoji Nishio , Ikuro Masuda
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L23/528 , H01L21/82 , H01L27/11807 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged adjacent to and in parallel with each other to form a basic cell line. A plurality of such basic cell lines are arranged in parallel with each other with a wiring region of a predetermined width being interleaved between adjacent basic cell lines.
摘要翻译：公开了一种半导体集成电路器件。在半导体衬底的一个主表面上形成至少具有基本晶体管器件的多个单元电池排列成一行以形成单元电池。这些单位细胞系中的至少两个彼此相邻并且平行地排列以形成基本细胞系。多个这样的基本细胞系被布置成彼此并联，具有预定宽度的布线区域在相邻的基本细胞系之间交错。

98. 发明授权

US08510629B2 Memory module on which regular chips and error correction chips are mounted 有权
标题翻译：内置模块，其上安装有常规芯片和纠错芯片
公开(公告)号：US08510629B2
公开(公告)日：2013-08-13
申请号：US12908512
申请日：2010-10-20
申请人： Wataru Tsukada , Shiro Harashima , Yoji Nishio
发明人： Wataru Tsukada , Shiro Harashima , Yoji Nishio
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , H03M13/13
摘要： Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.
摘要翻译：将其中存储用户数据的常规芯片封装和存储其中的纠错码的纠错芯片封装安装在模块基板上。模块基板在X方向上具有不同坐标的第一和第二安装区域，并且第二安装区域具有不同Y坐标的第三和第四安装区域。常规包装件相对地布置在模块基板的表面和背面上的第一安装区域中。纠错芯片封装相对地布置在模块基板的表面和背面上的第三安装区域中。缓冲用户数据和纠错码的存储器缓冲器布置在第四安装区域中。

99. 发明授权

US08347057B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US08347057B2
公开(公告)日：2013-01-01
申请号：US12805689
申请日：2010-08-13
申请人： Yoji Nishio , Takao Ono
发明人： Yoji Nishio , Takao Ono
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G06F13/1673
摘要： A memory buffer mounted on a memory module includes a pre-launch function of advancing outputs of address/command signal and a post-launch function of delaying outputs of control signal. A time step increment for pre/post-launch time adjustment is set to be equal to or finer than tCK/32 where tCK is one clock cycle.
摘要翻译：安装在存储器模块上的存储器缓冲器包括推进地址/命令信号输出的预启动功能和延迟控制信号输出的发射后功能。预启动/启动后时间调整的时间步长增量设置为等于或更小于tCK / 32，其中tCK是一个时钟周期。

100. 发明授权

US08064222B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US08064222B2
公开(公告)日：2011-11-22
申请号：US12113414
申请日：2008-05-01
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L23/66 , G06F1/184 , G06F1/185 , G06F1/186 , G11C5/025 , H01L21/6835 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2221/6834 , H01L2221/68368 , H01L2224/16 , H01L2924/01004 , H01L2924/0102 , H01L2924/01068 , H01L2924/13091 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/141 , H01L2924/00
摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
摘要翻译：包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。芯片组和COC DRAM之间的布线结构对于每个信号是相同的。因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式