专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08603924B2 Methods of forming gate dielectric material 有权
标题翻译：形成栅介质材料的方法
公开(公告)号：US08603924B2
公开(公告)日：2013-12-10
申请号：US13004309
申请日：2011-01-11
申请人： Liang-Gi Yao , Chia-Cheng Chen , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chia-Cheng Chen , Clement Hsingjen Wann
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/4983 , H01L21/28185 , H01L21/28211 , H01L21/283 , H01L29/49 , H01L29/51 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.
摘要翻译：形成栅极电介质材料的方法包括在衬底上形成氧化硅栅极层。用第一含臭氧气体处理氧化硅栅极层。在处理氧化硅栅极层之后，在经处理的氧化硅栅极层上形成高介电常数（高k）栅极电介质层。

92. 发明授权

US08097924B2 Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same 有权
标题翻译：具有高k栅极电介质和原位掺杂的选择性外延源极/漏极延伸的超浅结结MOSFET及其制造方法
公开(公告)号：US08097924B2
公开(公告)日：2012-01-17
申请号：US10872095
申请日：2004-06-18
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

93. 发明申请

US20110291205A1 HIGH-K GATE DIELECTRIC AND METHOD OF MANUFACTURE 有权
标题翻译：高K栅介质及其制造方法
公开(公告)号：US20110291205A1
公开(公告)日：2011-12-01
申请号：US13209493
申请日：2011-08-15
申请人： Chen-Hua Yu , Liang-Gi Yao
发明人： Chen-Hua Yu , Liang-Gi Yao
IPC分类号： H01L29/78
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.
摘要翻译：为高k栅极电介质和栅电极提供了一种器件和形成方法。形成高k电介质材料，并且在高k电介质材料上形成富硅膜。然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。然后通过受控的工艺在膜上形成导电材料以产生栅极导体。

94. 发明授权

US08003548B2 Atomic layer deposition 有权
标题翻译：原子层沉积
公开(公告)号：US08003548B2
公开(公告)日：2011-08-23
申请号：US12793346
申请日：2010-06-03
申请人： Chen-Hua Yu , Liang-Gi Yao
发明人： Chen-Hua Yu , Liang-Gi Yao
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/306 , H01L21/02052 , H01L21/02181 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/513 , H01L29/517
摘要： A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer.
摘要翻译：提供了一种用于形成原子沉积层的方法，其包括：（a）在衬底上执行第一水脉冲; （b）在羟基化底物上进行前体脉冲，其中前体与羟基反应并形成一层; （c）用惰性载气吹扫衬底; （d）将该层暴露于第二水脉冲至少约3秒，使得该层在其上具有最少70％的表面羟基; （e）用惰性载气吹扫该层; 和（f）重复步骤（b）至（e）以形成所得到的原子沉积层。

95. 发明授权

US07892961B2 Methods for forming MOS devices with metal-inserted polysilicon gate stack 有权
标题翻译：用金属插入多晶硅栅极叠层形成MOS器件的方法
公开(公告)号：US07892961B2
公开(公告)日：2011-02-22
申请号：US11809337
申请日：2007-05-31
申请人： Chen-Hua Yu , Cheng-Tung Lin , Liang-Gi Yao
发明人： Chen-Hua Yu , Cheng-Tung Lin , Liang-Gi Yao
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/3215 , H01L21/336
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。形成硅层的步骤包括原位掺杂第一杂质。（或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

96. 发明授权

US07892909B2 Polysilicon gate formation by in-situ doping 有权
标题翻译：通过原位掺杂形成多晶硅栅
公开(公告)号：US07892909B2
公开(公告)日：2011-02-22
申请号：US11729009
申请日：2007-03-28
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

97. 发明授权

US07851377B2 Chemical vapor deposition process 有权
标题翻译：化学气相沉积工艺
公开(公告)号：US07851377B2
公开(公告)日：2010-12-14
申请号：US11652209
申请日：2007-01-11
申请人： Chen-Hua Yu , Liang-Gi Yao
发明人： Chen-Hua Yu , Liang-Gi Yao
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/40 , C23C16/452 , C23C16/45531 , C23C16/45542 , H01L21/02148 , H01L21/02181 , H01L21/02277 , H01L21/3141 , H01L21/31604 , H01L21/31645
摘要： A chemical vapor deposition (CVD) method includes placing a semiconductor wafer into a reaction chamber; introducing a precursor into the reaction chamber; activating the precursor to a high-energy state using a non-direct plasma energy source; and reacting the precursor to form a film on the semiconductor wafer.
摘要翻译：化学气相沉积（CVD）方法包括将半导体晶片放入反应室中; 将前体引入反应室; 使用非直接等离子体能源将前体活化至高能态; 并使所述前体反应在所述半导体晶片上形成膜。

98. 发明授权

US07732878B2 MOS devices with continuous contact etch stop layer 有权
标题翻译：具有连续接触蚀刻停止层的MOS器件
公开(公告)号：US07732878B2
公开(公告)日：2010-06-08
申请号：US11583634
申请日：2006-10-18
申请人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/78
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823842 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.
摘要翻译：半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

99. 发明申请

US20080305646A1 Atomic layer deposition 审中-公开
标题翻译：原子层沉积
公开(公告)号：US20080305646A1
公开(公告)日：2008-12-11
申请号：US11808388
申请日：2007-06-08
申请人： Chen-Hua Yu , Liang-Gi Yao
发明人： Chen-Hua Yu , Liang-Gi Yao
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , H01L21/02052 , H01L21/02181 , H01L21/02192 , H01L21/306 , H01L21/3141 , H01L21/31645
摘要： An atomic layer deposition with hydroxylation pre-treatment is provided. The atomic layer deposition comprises the steps of (a) performing a hydroxylation pre-treatment on a silicon substrate to create a predetermined number of hydroxyl groups thereon; (b) performing a precursor pulse on the pre-treated silicon substrate, wherein the precursor react with the hydroxyl groups, forming a layer; (c) purging the silicon substrate with an inert carrier gas; (d) performing a water pulse on the layer sufficiently so as to create a predetermined number of hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b)˜(e) until the atomic layer deposition is completed. Each layer overlying the silicon substrate has a minimum of 70 percent surface hydroxyl groups.
摘要翻译：提供了具有羟基化预处理的原子层沉积。原子层沉积包括以下步骤：（a）在硅衬底上进行羟基化预处理以在其上产生预定数量的羟基; （b）在预处理的硅衬底上执行前体脉冲，其中前体与羟基反应形成一层; （c）用惰性载气吹扫硅衬底; （d）充分地在该层上进行水脉冲以在其上产生预定数量的羟基; （e）用惰性载气吹扫该层; 和（f）重复步骤（b）〜（e）直到原子层沉积完成。覆盖硅衬底的每个层具有至少70％的表面羟基。

100. 发明申请

US20080290416A1 HIGH-K METAL GATE DEVICES AND METHODS FOR MAKING THE SAME 审中-公开
标题翻译：高K金属门装置及其制造方法
公开(公告)号：US20080290416A1
公开(公告)日：2008-11-27
申请号：US11751403
申请日：2007-05-21
申请人： Chen-Hua Yu , Liang-Gi Yao , Cheng-Tung Lin
发明人： Chen-Hua Yu , Liang-Gi Yao , Cheng-Tung Lin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/26566 , H01L21/28035 , H01L21/28158 , H01L21/823828 , H01L21/823842 , H01L29/4916 , H01L29/518
摘要： A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections.
摘要翻译：在高k电介质层上形成功函数约4.3或4.4eV或更小的P金属材料层。通过引入添加剂如O，C，N，Si等将N金属层的一部分转化为P金属材料，以产生具有约4.7或4.8eV或更大功函数的P金属材料。使用这种技术可以将TaC膜转变为TaCO，TaCN或TaCON的材料。然后使用单一图案化操作来构图包括原始N-金属部分和转换的P金属部分的材料层，以同时从未转换的N金属部分和转换的P金属部分形成半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式