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91. 发明授权

US07112493B2 Method of making non-volatile field effect devices and arrays of same 有权
标题翻译：制造非易失性场效应器件及其阵列的方法
公开(公告)号：US07112493B2
公开(公告)日：2006-09-26
申请号：US10864751
申请日：2004-06-09
申请人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
发明人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
IPC分类号： H01L21/8234
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. An electromechanically-deflectable, nanotube switching element is formed over the field effect device. Terminals and corresponding interconnect are provided to correspond to each of the source, drain and gate such that the nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal, and such that the others of said source, drain and gate are directly connected to their corresponding terminals.
摘要翻译：制造非易失性场效应器件及其阵列的方法。在一个实施例中，制造非易失性场效应器件的方法包括提供其中形成有场效应器件的衬底。场效应器件包括在源极和漏极之间具有场可调通道的源极，漏极和栅极。在场效应器件上形成机电偏转的纳米管开关元件。提供端子和相应的互连件以对应于源极，漏极和栅极中的每一个，使得纳米管开关元件电气地定位在源极，漏极和栅极之间及其对应的端子之间，并且使得其他源极，漏极并且门直接连接到其相应的端子。

92. 发明授权

US06982903B2 Field effect devices having a source controlled via a nanotube switching element 有权
标题翻译：通过纳米管开关元件控制源极的场效应器件
公开(公告)号：US06982903B2
公开(公告)日：2006-01-03
申请号：US10864045
申请日：2004-06-09
申请人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal , Frank Guo
发明人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal , Frank Guo
IPC分类号： G11C11/00
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Field effect devices having a source controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The drain region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the source region and a terminal corresponding to the source region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the source region and its corresponding terminal. When the nanotube switching element is in the closed state, the channel conductivity and operation of the device is responsive to electrical stimulus at the terminals corresponding to the source and drain regions and the gate structure.
摘要翻译：通过纳米管开关元件控制源极的场效应器件。在一个实施例中，场效应器件包括第一半导体类型的源极区域和漏极区域以及设置在第二半导体类型之间的沟道区域。漏极区域连接到相应的端子。栅极结构设置在沟道区域上并连接到相应的端子。纳米管开关元件响应于第一控制端子和第二控制端子，并且电源定位在源极区域和与源极区域对应的端子之间。纳米管开关元件在机电上可操作为打开和关闭状态之一，从而打开或关闭源极区域与其对应端子之间的电连通路径。当纳米管开关元件处于闭合状态时，器件的沟道导电性和操作响应于对应于源极和漏极区域以及栅极结构的端子处的电刺激。

93. 发明授权

US06972220B2 Structures and methods of anti-fuse formation in SOI 失效
标题翻译： SOI中抗熔丝形成的结构和方法
公开(公告)号：US06972220B2
公开(公告)日：2005-12-06
申请号：US10366298
申请日：2003-02-12
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L21/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

94. 发明授权

US06944054B2 NRAM bit selectable two-device nanotube array 失效
标题翻译： NRAM位可选双器件纳米管阵列
公开(公告)号：US06944054B2
公开(公告)日：2005-09-13
申请号：US10810962
申请日：2004-03-26
申请人： Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
发明人： Thomas Rueckes , Brent M. Segal , Bernhard Vogeli , Darren K. Brock , Venkatachalam C. Jaiprakash , Claude L. Bertin
IPC分类号： G11C13/02 , G11C23/00 , G11C11/34
CPC分类号： G11C23/00 , B82Y10/00 , G11C13/025 , Y10S977/943
摘要： A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.
摘要翻译：非易失性存储器阵列包括多个存储器单元，每个单元接收位线，字线和释放线。每个存储单元包括单元选择晶体管和具有第一，第二和第三节点的恢复晶体管。每个单元还包括机电偏转开关，其位置表示单元的逻辑状态。每个单元都可以进行读和写操作。

95. 发明授权

US06177818B1 Complementary depletion switch body stack off-chip driver 失效
标题翻译：互补耗尽开关体堆栈片外驱动
公开(公告)号：US06177818B1
公开(公告)日：2001-01-23
申请号：US09303508
申请日：1999-04-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
IPC分类号： H03B2100
CPC分类号： H03K19/09482 , H03K19/00361 , H03K19/018521
摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.
摘要翻译：包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。在另一个实施例中，添加了反射/过冲传感器60。传感器的输出连接到耗尽PFET和NFET的主体。来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

96. 发明授权

US6097243A Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode 有权
标题翻译：使用低功耗模式降低集成半导体器件功耗的装置和方法
公开(公告)号：US6097243A
公开(公告)日：2000-08-01
申请号：US159861
申请日：1998-09-24
申请人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
IPC分类号： G05F1/08 , G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。

97. 发明授权

US6060746A Power transistor having vertical FETs and method for making same 失效
标题翻译：具有垂直FET的功率晶体管及其制造方法
公开(公告)号：US6060746A
公开(公告)日：2000-05-09
申请号：US798663
申请日：1997-02-11
申请人： Claude L. Bertin , Jeffrey P. Gambino , Jack A. Mandelman
发明人： Claude L. Bertin , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A power transistor having of a plurality of vertical MOSFET devices combined in parallel to achieve high-performance operation and methods of fabricating this device.
摘要翻译：具有并联组合的多个垂直MOSFET器件以实现高性能操作的功率晶体管和制造该器件的方法。

98. 发明授权

US5617351A Three-dimensional direct-write EEPROM arrays and fabrication methods 失效
标题翻译：三维直写EEPROM阵列及制作方法
公开(公告)号：US5617351A
公开(公告)日：1997-04-01
申请号：US464018
申请日：1995-06-05
申请人： Claude L. Bertin , Donelli J. DiMaria , Makoto Miyakawa , Yoshinori Sakaue
发明人： Claude L. Bertin , Donelli J. DiMaria , Makoto Miyakawa , Yoshinori Sakaue
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/7882
摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.
摘要翻译：公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。存储单元用于制造具有高集成度密度的非易失性直写EEPROM阵列。典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽。多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门和编程门。优选地，设置在每个浮动栅极与其相关联的编程和调用栅极之间的富硅电介质（例如富氧氧化物）。公开了源极扩散和隔离源扩散实施例。此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。

99. 发明授权

US5567653A Process for aligning etch masks on an integrated circuit surface using electromagnetic energy 失效
标题翻译：使用电磁能量在集成电路表面上对准蚀刻掩模的工艺
公开(公告)号：US5567653A
公开(公告)日：1996-10-22
申请号：US306042
申请日：1994-09-14
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L21/027 , H01L21/31
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

100. 发明授权

US5532519A Cube wireability enhancement with chip-to-chip alignment and thickness control 失效
标题翻译：具有芯片对芯片对齐和厚度控制的立方线可提升性
公开(公告)号：US5532519A
公开(公告)日：1996-07-02
申请号：US375770
申请日：1995-01-20
申请人： Claude L. Bertin , John E. Cronin , David J. Perlman
发明人： Claude L. Bertin , John E. Cronin , David J. Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L23/538
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

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