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    • 91. 发明授权
    • Semiconductor device having redundancy circuit
    • 具有冗余电路的半导体器件
    • US06909647B2
    • 2005-06-21
    • US10813240
    • 2004-03-31
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • G11C5/00G11C7/00G11C8/00G11C29/00
    • G11C29/80G11C29/785G11C29/808
    • A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    • 半导体存储器具有冗余电路的缺陷恢复方案。 存储器中的存储器阵列具有多个字线,多个位线,备用位线和多个存储器单元。 冗余电路包括具有可编程元件的一个或多个比较电路,其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息(数据),例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息(数据)进行比较。 在此比较的基础上,进行适当的缺陷恢复。
    • 92. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20050073895A1
    • 2005-04-07
    • US10636558
    • 2003-08-08
    • Hideharu YahataMasashi HoriguchiYoshikazu SaitohYasushi Kawase
    • Hideharu YahataMasashi HoriguchiYoshikazu SaitohYasushi Kawase
    • G11C11/403G11C7/00G11C11/34G11C11/401G11C11/406
    • G11C11/40615G11C11/406G11C11/408G11C2211/4061
    • With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
    • 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的,实现高速存储器周期时间,提供了一种具有时间多路复用模式的伪静态RAM,当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令,每个存储器单元需要周期性地保持存储器信息的刷新操作,或者写入其中的存储器信息,执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作, 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器,以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
    • 93. 发明授权
    • Semiconductor memory having dynamic memory cells and a redundancy relief circuit
    • 具有动态存储单元的半导体存储器和冗余消除电路
    • US06762963B2
    • 2004-07-13
    • US10192615
    • 2002-07-11
    • Yoshihiko InoueHisashi MotomuraMasashi Horiguchi
    • Yoshihiko InoueHisashi MotomuraMasashi Horiguchi
    • G11C700
    • G11C11/406
    • A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.
    • 一种能够减少刷新周期时间的半导体存储器,其包括在多个正常字线和多个位线的预定交点处提供的正常存储器单元以及冗余字线和多个位线的冗余存储器单元,冗余消除电路评估每个 用于存储器操作的内部地址信号和刷新地址信号对应于多个正常字线的缺陷字线的地址。 地址选择电路根据评估结果将缺陷字线切换成冗余字线。 然后,冗余解除电路评估添加到刷新地址信号的刷新地址是否对应于缺陷地址,并且在刷新期间,地址选择电路根据前一周期的评估结果选择正常或冗余字线。
    • 94. 发明授权
    • Semiconductor device having redundancy circuit
    • 具有冗余电路的半导体器件
    • US06577544B2
    • 2003-06-10
    • US09992001
    • 2001-11-26
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • G11C700
    • G11C29/80G11C29/785G11C29/808
    • A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    • 半导体存储器具有冗余电路的缺陷恢复方案。 存储器中的存储器阵列具有多个字线,多个位线,备用位线和多个存储器单元。 冗余电路包括具有可编程元件的一个或多个比较电路,其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息(数据),例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息(数据)进行比较。 在此比较的基础上,进行适当的缺陷恢复。
    • 99. 发明授权
    • Semiconductor memory having redundancy circuit
    • 具有冗余电路的半导体存储器
    • US5815448A
    • 1998-09-29
    • US825605
    • 1997-03-31
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • Masashi HoriguchiJun EtohMasakazu AokiKiyoo Itoh
    • G11C5/00G11C7/00G11C8/00G11C29/00
    • G11C29/80G11C29/785G11C29/808
    • A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
    • 引入冗余技术用于半导体存储器,更具体地,涉及具有16兆位或更多存储容量的动态随机存取存储器(DRAM)的冗余技术。 在这样的DRAM中,存储器阵列被分成存储器垫。 根据本技术的冗余技术,对于包含具有多个字线的存储器阵列的半导体存储器,配置成在字线和位线之间形成2级交叉的多位位线,位于 提供了两级交叉中的期望的和备用位线,提供了一种冗余电路,其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与所存储的缺陷地址进行比较的存储器,以及选择电路 包括用于根据比较结果用备用位线替换有缺陷位线的逻辑“或”门。 每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。