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91. 发明申请

US20130134490A1 LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR 有权
公开(公告)号：US20130134490A1
公开(公告)日：2013-05-30
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

92. 发明申请

US20110272702A1 ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 有权
标题翻译： EDRAM的增强电容深度电容器
公开(公告)号：US20110272702A1
公开(公告)日：2011-11-10
申请号：US12775532
申请日：2010-05-07
申请人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
发明人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

93. 发明授权

US08592266B2 Replacement gate MOSFET with a high performance gate electrode 有权
公开(公告)号：US08592266B2
公开(公告)日：2013-11-26
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

94. 发明授权

US08535544B2 Structure and method to form nanopore 有权
标题翻译：结构和方法形成纳米孔
公开(公告)号：US08535544B2
公开(公告)日：2013-09-17
申请号：US12843228
申请日：2010-07-26
申请人： Chengwen Pei , Zhengwen Li
发明人： Chengwen Pei , Zhengwen Li
IPC分类号： B44C1/22 , B82Y40/00
CPC分类号： G01N33/48721 , B32B3/266 , B81B2201/058 , B81B2203/0384 , B81C1/00087 , C30B33/10 , Y10T428/249975
摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.
摘要翻译：提供了制造具有纳米尺度孔的材料的方法。在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。

95. 发明申请

US20120275208A1 RELIABLE ELECTRICAL FUSE WITH LOCALIZED PROGRAMMING AND METHOD OF MAKING THE SAME 有权
标题翻译：具有本地化编程的可靠电气保险丝及其制造方法
公开(公告)号：US20120275208A1
公开(公告)日：2012-11-01
申请号：US13095164
申请日：2011-04-27
申请人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： G11C17/16 , H01L21/8238 , H01L23/62
CPC分类号： H01L23/62 , G11C17/16 , H01L21/02532 , H01L21/28518 , H01L21/76886 , H01L21/823814 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.
摘要翻译：电熔丝在半导体衬底的表面上具有阳极接触。电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。该连接件包括半导体层和硅化物层。硅化物层延伸超过阳极接触。硅化物层的另一端延伸超过阴极接触。在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

96. 发明申请

US20120021204A1 STRUCTURE AND METHOD TO FORM NANOPORE 有权
标题翻译：结构和方法形成纳米
公开(公告)号：US20120021204A1
公开(公告)日：2012-01-26
申请号：US12843228
申请日：2010-07-26
申请人： Chengwen Pei , Zhengwen Li
发明人： Chengwen Pei , Zhengwen Li
IPC分类号： B32B3/26 , C23F1/02
CPC分类号： G01N33/48721 , B32B3/266 , B81B2201/058 , B81B2203/0384 , B81C1/00087 , C30B33/10 , Y10T428/249975
摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.
摘要翻译：提供了制造具有纳米尺度孔的材料的方法。在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。

97. 发明授权

US09006801B2 Method for forming metal semiconductor alloys in contact holes and trenches 有权
标题翻译：在接触孔和沟槽中形成金属半导体合金的方法
公开(公告)号：US09006801B2
公开(公告)日：2015-04-14
申请号：US13013081
申请日：2011-01-25
申请人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L21/285 , H01L21/336 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/311 , H01L21/768
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要翻译：提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

98. 发明申请

US20120104469A1 REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE 有权
标题翻译：具有高性能门电极的替代栅极MOSFET
公开(公告)号：US20120104469A1
公开(公告)日：2012-05-03
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
摘要翻译：在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

99. 发明授权

US08981523B2 Programmable fuse structure and methods of forming 有权
标题翻译：可编程熔丝结构和成型方法
公开(公告)号：US08981523B2
公开(公告)日：2015-03-17
申请号：US13419877
申请日：2012-03-14
申请人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： H01L23/52 , H01L23/525 , H01L23/532 , H01L27/115
CPC分类号： H01L23/5256 , H01L23/53204 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.
摘要翻译：公开了形成电可编程熔丝（e熔丝）结构和电熔体结构的方法。形成e熔丝结构的各种实施例包括：形成虚拟多晶硅结构以接触硅结构的表面，所述虚设多晶硅结构仅延伸所述硅结构的长度的一部分; 以及将所述硅结构的表面的无障碍部分转化为硅化物以在两个端部区域之间形成所述硅化物的薄化带。

100. 发明授权

US08927432B2 Continuously scalable width and height semiconductor fins 有权
标题翻译：连续可调的宽度和高度半导体鳍片
公开(公告)号：US08927432B2
公开(公告)日：2015-01-06
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.
摘要翻译：通过为鳍式场效应晶体管所采用的半导体鳍片的物理尺寸提供两个独立的变量，可以为鳍式场效应晶体管提供任意和连续的可变电流。在掩埋绝缘体层上的半导体层上形成凹陷区域。在半导体层上形成电介质盖层。在电介质盖层上形成一次性心轴结构，并且围绕一次性心轴结构形成间隔结构。在掩蔽离子注入期间，选择的间隔结构可以在结构上受损。使用蚀刻以比未损坏的间隔物结构更大的蚀刻速率去除结构损坏的间隔物结构。在去除一次性心轴结构之后，将半导体层图案化成具有不同高度和/或不同宽度的多个半导体翅片。随后可以形成具有不同宽度和/或高度的鳍场效应晶体管。

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