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91. 发明申请

US20080001646A1 Thermally stable semiconductor power device 有权
标题翻译：热稳定的半导体功率器件
公开(公告)号：US20080001646A1
公开(公告)日：2008-01-03
申请号：US11480041
申请日：2006-06-30
申请人： Sik K. Lui , Anup Bhalla , Sanjay Havanur
发明人： Sik K. Lui , Anup Bhalla , Sanjay Havanur
IPC分类号： H03K17/687
CPC分类号： H01L29/7813 , H01L27/0255 , H01L29/0696 , H01L29/7803 , H01L29/7804 , H03K17/08122 , H03K2017/0806
摘要： A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.
摘要翻译：半导体功率器件包括提供栅极信号的电路，其中栅极信号具有负温度系数的栅极驱动电压，用于随温度升高而降低栅极驱动电压，由此半导体功率器件的净Ids温度系数小于或等于零。在示例性实施例中，栅极电压驱动器包括具有连接在半导体功率器件的栅极和源极之间的正向正向电压温度系数的二极管。在另一个实施例中，栅极电压与作为与半导体功率器件的集成电路的一部分制造的半导体功率器件集成。

92. 发明申请

US20070194374A1 Shielded gate trench (SGT) MOSFET devices and manufacturing processes 有权
标题翻译：屏蔽栅极沟槽（SGT）MOSFET器件和制造工艺
公开(公告)号：US20070194374A1
公开(公告)日：2007-08-23
申请号：US11356944
申请日：2006-02-17
申请人： Anup Bhalla , Sik K. Lui
发明人： Anup Bhalla , Sik K. Lui
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.
摘要翻译：本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。构成活性单元的单元中的至少一个具有与沟槽栅极相邻设置的源极区域，该沟槽栅极电连接到栅极焊盘并围绕电池。沟槽栅极还具有填充有栅极材料的底部屏蔽电极，栅极材料设置在沟槽栅极下方并与沟槽栅极绝缘。构成由沟槽围绕的源极接触单元中的至少一个具有用作源极连接沟槽的部分的单元填充有栅极材料，用于电连接底部屏蔽电极和直接设置在源极连接沟槽顶部的源极金属源连接沟槽。半导体功率器件还包括设置在半导体功率器件的顶部上的绝缘保护层，其具有在源极区域的顶部上的多个源极开口和设置用于电连接到源极金属的源极连接沟槽和至少提供的栅极开口用于将栅极焊盘电连接到沟槽栅极。

93. 发明申请

US20070182435A1 Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests 有权
标题翻译：执行晶圆级无钳位感应开关（UIS）测试的配置和方法
公开(公告)号：US20070182435A1
公开(公告)日：2007-08-09
申请号：US11300082
申请日：2005-12-14
申请人： Sik Lui , Anup Bhalla
发明人： Sik Lui , Anup Bhalla
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/2831 , G01R31/327
摘要： This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET. Furthermore, the test circuit further includes a timing and make before break (MBB) circuit for receiving an MOSFET failure signal from the MOSFET failure detection circuit and for controlling the first and second switches for switching off a power supply to the MOSFET device upon a detection of an UIS failure under the UIS test to prevent damages to a probe
摘要翻译：本发明公开了一种用于对由栅极驱动器驱动的金属氧化物半导体场效应晶体管（MOSFET）器件执行未钳位电感测试的电路。该电路包括电流检测电路，用于测量从栅极驱动器输入到MOSFET器件的脉冲宽度增加而增加的未钳位电感测试（UIS）电流，其中提供电流检测电路以在栅极驱动器达到预定义的UIS电流。测试电路还包括连接到MOSFET器件的漏极端子的MOSFET故障检测电路，用于测量在UIS测试期间检测MOSFET故障的漏极电压变化。测试电路还包括用于将MOSFET器件的电源接通/断开的第一开关和连接在MOSFET的漏极和源极端子之间的第二开关。此外，测试电路还包括用于从MOSFET故障检测电路接收MOSFET故障信号的定时和断开前（MBB）电路，并且用于在检测时控制用于关断到MOSFET器件的电源的第一和第二开关在统计研究所测试下的统计研究所失败，以防止探针受损

94. 发明授权

US07208818B2 Power semiconductor package 有权
标题翻译：功率半导体封装
公开(公告)号：US07208818B2
公开(公告)日：2007-04-24
申请号：US10896375
申请日：2004-07-20
申请人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tian Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tian Zhang
IPC分类号： H01L23/495
CPC分类号： H01L23/49562 , H01L23/492 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0603 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/4943 , H01L2224/73221 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0106 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2076 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.
摘要翻译：一种半导体封装，包括具有多个引线的相对厚的引线框架和第一引线框架焊盘，所述第一引线框焊盘包括与其连接的管芯，将所述管芯连接到所述多个引线的接合线，所述接合线为铝，以及封装模具的树脂体，接合线和引线框架的至少一部分。

95. 发明申请

US20060180855A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20060180855A1
公开(公告)日：2006-08-17
申请号：US11056346
申请日：2005-02-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

96. 发明申请

US20060091505A1 Low cost power MOSFET with current monitoring 有权
公开(公告)号：US20060091505A1
公开(公告)日：2006-05-04
申请号：US10979410
申请日：2004-11-02
申请人： Sik Lui , Anup Bhalla
发明人： Sik Lui , Anup Bhalla
IPC分类号： H01L23/495
CPC分类号： H01L24/91 , H01L23/49575 , H01L24/48 , H01L25/16 , H01L29/7834 , H01L2224/16 , H01L2224/48091 , H01L2224/73257 , H01L2924/00014 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/19107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor integrated circuit package having a common source current sensing circuit includes a main die having an integrated circuit, the main die including a source bonding pad and a gate bonding pad disposed on an upper surface, a leadframe having a leadframe pad disposed under the main die, and a monitoring die including a source bonding pad and a gate bonding pad disposed on an upper surface, the monitoring die being coupled to the main die in such manner that the main die source bonding pad is coupled to the monitoring die source bonding pad and the main die gate bonding pad is coupled to the monitoring die gate bonding pad and such that the main die and monitoring die upper surfaces are adjacent to one another.

97. 发明授权

US06275093B1 IGBT gate drive circuit with short circuit protection 失效
标题翻译： IGBT栅极驱动电路具有短路保护功能
公开(公告)号：US06275093B1
公开(公告)日：2001-08-14
申请号：US09030871
申请日：1998-02-25
申请人： Sampat Singh Shekhawat , Jon Gladish , Anup Bhalla
发明人： Sampat Singh Shekhawat , Jon Gladish , Anup Bhalla
IPC分类号： H03K17687
CPC分类号： H03K17/0828
摘要： An IGBT gate driver circuit includes means for detecting when the collector-to-emitter voltage (Vce) of a turned-on IGBT, intended to be operated in the saturation region, increases above a preset level, indicative of a fault condition, such as a short circuit. In response to such an increase in the Vce of a turned on IGBT, the IGBT is turned-off in two steps. First, the turn-on gate drive is decreased to a level that is still above the threshold (turn-on) voltage of the IGBT in order to decrease the current flowing through the IGBT and hence, the peak power dissipation. This decrease in the current through the IGBT and the peak power dissipation increases the length of time the IGBT can withstand a fault condition such as a short circuit. Then, after decreasing the gate drive to the IGBT, the gate drive is gradually decreased until the IGBT is completely turned off.
摘要翻译： IGBT栅极驱动器电路包括用于检测旨在在饱和区域中操作的导通IGBT的集电极 - 发射极电压（Vce）何时增加到指示故障状态的预设电平以上的装置，例如短路。响应于导通IGBT的Vce的这种增加，IGBT分两个阶段关断。首先，导通栅极驱动被降低到仍然高于IGBT的阈值（导通）电压的电平，以便减小流过IGBT的电流，并因此降低峰值功耗。通过IGBT的电流的降低和峰值功率耗散增加了IGBT能够经受诸如短路的故障状态的时间长度。然后，在将栅极驱动减少到IGBT之后，栅极驱动逐渐减小，直到IGBT完全关断。

98. 发明授权

US10103240B2 Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode 有权
公开(公告)号：US10103240B2
公开(公告)日：2018-10-16
申请号：US13763675
申请日：2013-02-10
申请人： Madhur Bobde , Lingpeng Guann , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guann , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/66
摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

99. 发明授权

US09741851B2 Trench junction barrier controlled Schottky 有权
公开(公告)号：US09741851B2
公开(公告)日：2017-08-22
申请号：US13892312
申请日：2013-05-13
申请人： Sik K Lui , Anup Bhalla
发明人： Sik K Lui , Anup Bhalla
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78 , H01L29/872 , H01L29/06
CPC分类号： H01L29/7839 , H01L29/0619 , H01L29/0623 , H01L29/66143 , H01L29/66712 , H01L29/7806 , H01L29/7813 , H01L29/872
摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

100. 发明申请

US20170125514A9 MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES 审中-公开
公开(公告)号：US20170125514A9
公开(公告)日：2017-05-04
申请号：US14298922
申请日：2014-06-08
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/266 , H01L21/324 , H01L29/10
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

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