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1. 发明授权

US07208818B2 Power semiconductor package 有权
标题翻译：功率半导体封装
公开(公告)号：US07208818B2
公开(公告)日：2007-04-24
申请号：US10896375
申请日：2004-07-20
申请人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tian Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tian Zhang
IPC分类号： H01L23/495
CPC分类号： H01L23/49562 , H01L23/492 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0603 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/4943 , H01L2224/73221 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0106 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2076 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.
摘要翻译：一种半导体封装，包括具有多个引线的相对厚的引线框架和第一引线框架焊盘，所述第一引线框焊盘包括与其连接的管芯，将所述管芯连接到所述多个引线的接合线，所述接合线为铝，以及封装模具的树脂体，接合线和引线框架的至少一部分。

2. 发明授权

US07633140B2 Inverted J-lead for power devices 有权
标题翻译：功率器件的倒置J型引线
公开(公告)号：US07633140B2
公开(公告)日：2009-12-15
申请号：US10732181
申请日：2003-12-09
申请人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tiang Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik K. Lui , Yueh-Se Ho , Mike F. Chang , Xiao Tiang Zhang
IPC分类号： H01L23/495
CPC分类号： H01L24/48 , H01L23/49555 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/49 , H01L24/73 , H01L2224/05552 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/32245 , H01L2224/371 , H01L2224/37599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73265 , H01L2224/84801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/0106 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.
摘要翻译：半导体封装包括具有多个引线和引线框架焊盘的引线框架，所述引线框架焊盘包括耦合到其上的管芯，所述多个引线中的至少一个引线具有相对于所述封装的底表面向上倾斜的外部部分将模具连接到多个引线的金属连接器以及封装模具，金属连接器和引线框架的至少一部分的树脂体。

3. 发明授权

US08169062B2 Integrated circuit package for semiconductior devices with improved electric resistance and inductance 有权
标题翻译：具有改善电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08169062B2
公开(公告)日：2012-05-01
申请号：US13114063
申请日：2011-05-24
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/495 , H01L23/48 , H01L29/40 , H01L23/52
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

4. 发明申请

US20090014853A1 Integrated circuit package for semiconductior devices with improved electric resistance and inductance 有权
标题翻译：具有改善电阻和电感的半导体器件的集成电路封装
公开(公告)号：US20090014853A1
公开(公告)日：2009-01-15
申请号：US12215049
申请日：2008-06-23
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/495
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

5. 发明授权

US07391100B2 Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area 有权
标题翻译：用于半导体器件的集成电路封装具有减少的引线框焊盘和增加的焊接面积
公开(公告)号：US07391100B2
公开(公告)日：2008-06-24
申请号：US10972746
申请日：2004-10-25
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/48 , H01L23/495 , H01L23/50 , H01L23/485 , H01L21/02
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种具有引线框架（108）的半导体集成电路封装，该引线框架（108）包括设置在管芯（100）下方的引线框焊盘（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和管芯（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。该集成电路适用于MOSFET器件，并且焊接金属区域（101a）用于源极端子（101）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

6. 发明申请

US20110221005A1 Integrated circuit package for semiconductior devices with improved electric resistance and inductance 有权
标题翻译：具有改善电阻和电感的半导体器件的集成电路封装
公开(公告)号：US20110221005A1
公开(公告)日：2011-09-15
申请号：US13114063
申请日：2011-05-24
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L27/092
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the s bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal, resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。焊接金属区域（101a）的增加增加了金属区域（101a）和管芯（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果不最大化则增加，从而可以更快地消散热量并且减少外部端子的电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

7. 发明授权

US07183616B2 High speed switching MOSFETS using multi-parallel die packages with/without special leadframes 有权
标题翻译：高速开关MOSFET使用具有/不具有特殊引线框架的多并联芯片封装
公开(公告)号：US07183616B2
公开(公告)日：2007-02-27
申请号：US10208275
申请日：2002-07-30
申请人： Anup Bhalla , Sik K Lui , Leeshawn Luo , Yueh-Se Ho
发明人： Anup Bhalla , Sik K Lui , Leeshawn Luo , Yueh-Se Ho
IPC分类号： H01L23/62 , H01L29/94 , H01L29/76 , H01L31/119 , H01L31/113 , H01L23/34 , H01L23/50
CPC分类号： H01L24/06 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01074 , H01L2924/01079 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/20755 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.
摘要翻译：本发明公开了一种通过在组件中封装几个并联和分离的MOSFET芯片来配置功率MOSFET封装的方法。该方法还包括将这些MOSFET芯片中的每一个上的栅极焊盘与低电阻栅极总线连接的步骤。封装电阻和电感显着降低，开关速度和散热明显提高。

8. 发明授权

US08067822B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08067822B2
公开(公告)日：2011-11-29
申请号：US12215049
申请日：2008-06-23
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/52 , H01L23/485 , H01L23/495
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

9. 发明授权

US06841852B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US06841852B2
公开(公告)日：2005-01-11
申请号：US10189333
申请日：2002-07-02
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/48
CPC分类号： H01L24/85 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

10. 发明申请

US20080211070A1 Flip chip contact (FCC) power package 有权
标题翻译：倒装芯片接触（FCC）电源封装
公开(公告)号：US20080211070A1
公开(公告)日：2008-09-04
申请号：US11894240
申请日：2008-03-31
申请人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
发明人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
IPC分类号： H01L23/495
CPC分类号： H01L29/7813 , H01L24/33 , H01L29/045 , H01L29/4236 , H01L29/66734 , H01L29/7811 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.
摘要翻译：本发明公开了一种功率器件封装，用于容纳，保护和提供功率晶体管的电触头。功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。功率晶体管具有附接到顶部引线框架的底部漏极接触。顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。在另一个实施方案中，导电环氧树脂或粘合剂层，焊膏，碳糊或其它类型的附着剂用于将功率晶体管附接到顶引线框架和底引线框架之一的直接无凸起。

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