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91. 发明授权

US06015750A Method for improving visibility of alignment target in semiconductor processing 失效
标题翻译：用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US06015750A
公开(公告)日：2000-01-18
申请号：US7694
申请日：1998-01-15
申请人： James A. Bruce , Steven John Holmes , Robert K. Leidy
发明人： James A. Bruce , Steven John Holmes , Robert K. Leidy
IPC分类号： H01L23/544 , G01B11/27
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译：公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。

92. 发明授权

US5972570A Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效
公开(公告)号：US5972570A
公开(公告)日：1999-10-26
申请号：US895748
申请日：1997-07-17
申请人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
发明人： James A. Bruce , Steven J. Holmes , Robert K. Leidy , Walter E. Mlynko , Edward W. Sengle
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , G03F7/26
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

93. 发明授权

US5874778A Embedded power and ground plane structure 失效
标题翻译：嵌入式电源和接地平面结构
公开(公告)号：US5874778A
公开(公告)日：1999-02-23
申请号：US873102
申请日：1997-06-11
申请人： Arup Bhattacharyya , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert K. Leidy
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/528 , H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/3011
摘要： A device architecture with embedded planar conductive ground and power planes in the device architecture. The apparatus includes a first conductive plane, a second conductive plane, a signal plane disposed between the first and second conductive planes, and a logic level disposed adjacent the first conductive plane and connected to the signal plane through at least one via in the conductive plane. The apparatus also includes a built-in alignment scheme. The invention includes a method for making the device and alignment architectures.
摘要翻译：在器件架构中具有嵌入式平面导电接地和电源平面的器件架构。该装置包括第一导电平面，第二导电平面，设置在第一和第二导电平面之间的信号平面以及与第一导电平面相邻设置并通过导电平面中的至少一个通孔连接到信号平面的逻辑电平。该装置还包括内置的对准方案。本发明包括一种用于制造该装置和对准架构的方法。

94. 发明授权

US5811870A Antifuse structure 失效
标题翻译：防腐结构
公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

95. 发明授权

US5760483A Method for improving visibility of alignment targets in semiconductor processing 失效
标题翻译：用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US5760483A
公开(公告)日：1998-06-02
申请号：US772709
申请日：1996-12-23
申请人： James A. Bruce , Steven John Holmes , Robert K. Leidy
发明人： James A. Bruce , Steven John Holmes , Robert K. Leidy
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译：公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。

96. 发明授权

US5552718A Electrical test structure and method for space and line measurement 失效
标题翻译：空间和线路测量的电气测试结构和方法
公开(公告)号：US5552718A
公开(公告)日：1996-09-03
申请号：US368181
申请日：1995-01-04
申请人： James A. Bruce , Michael S. Hibbs , Robert K. Leidy
发明人： James A. Bruce , Michael S. Hibbs , Robert K. Leidy
IPC分类号： G01R31/26
CPC分类号： G01R31/26
摘要： This describes a test pattern and method for measuring dimensional characteristics of features formed on a surface. This is realized and provided by forming a space, defined by the feature, in intersecting relationship with a pair of conductive lines of a test pattern configuration such that the lines are altered at the intersection with the space in accordance with the dimensions of that space, measuring the resistance of at least one of the lines in a region remote from the intersection with the space and the resistance of each line in the region of its intersection with the space, and comparing the resistance of the remote region with the resistances for the region of each of the lines where they intersect the space to thereby establish the position of, and at least one dimension of that space. A test structure wherein the spaced lines intersect the longitudinal ends of the space is utilized for determining the length and the longitudinal position of the space, and a test structure where lines intersect the lateral edges of the space is utilized for determining the width of and the lateral position of the space. For measuring the dimensional characteristics of a line feature, the above noted patterns are utilized, after first replicating the line as a space.
摘要翻译：这描述了用于测量在表面上形成的特征的尺寸特性的测试图案和方法。这通过以与测试图案配置的一对导线相交的方式形成由特征限定的空间来实现并提供，使得根据该空间的尺寸在与空间的交叉处改变线，测量远离与该空间相交的区域的空间和电阻的区域中的至少一条线路的电阻，并将该偏移区域的电阻与该区域的电阻进行比较其中它们与空间相交的每条线，从而建立该空间的位置和至少一个维度。用于确定空间的长度和纵向位置的测量结构，其中与空间的纵向端部相交的间隔线用于确定空间的横向边缘的线和与该空间的横向边缘相交的测试结构，横向位置的空间。为了测量线特征的尺寸特征，在首先将线复制为空间之后，利用上述图案。

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