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91. 发明授权

US6137145A Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon 有权
标题翻译：半导体形貌包括集成了多层多晶硅层的集成电路栅极导体
公开(公告)号：US6137145A
公开(公告)日：2000-10-24
申请号：US237773
申请日：1999-01-26
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L21/8234 , H01K29/76
CPC分类号： H01L21/82345
摘要： A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.
摘要翻译：提供包括并入双多晶硅层的集成电路栅极导体的半导体形貌。半导体形貌包括半导体衬底。第一栅极导体布置在第一栅极电介质上并位于半导体衬底之上，并且第二栅极导体布置在第二栅极电介质上并位于半导体衬底之上。半导体衬底可以包含通过场区域与第二有源区域横向分离的第一有源区域。第一栅极导体可以布置在第一有源区内，并且第二栅极导体可以布置在第二有源区内。每个栅极导体优选地包括布置在第一多晶硅层部分上的第二多晶硅层部分。第一栅极导体和第二栅极导体的厚度优选相等。第一栅极导体可以掺杂有第一掺杂剂，其通过多晶硅具有比掺杂第二栅极导体的第二掺杂物更低的扩散速率。第二栅极导体的第二多晶硅层部分基本上没有注入的掺杂剂。

92. 发明授权

US08190391B2 Determining die performance by incorporating neighboring die performance metrics 有权
标题翻译：通过结合相邻的模具性能指标来确定模具性能
公开(公告)号：US08190391B2
公开(公告)日：2012-05-29
申请号：US11692989
申请日：2007-03-29
申请人： Daniel Kadosh , Gregory A. Cherry , Carl I. Bowen , Luis De La Fuente , Rajesh Vijayaraghavan
发明人： Daniel Kadosh , Gregory A. Cherry , Carl I. Bowen , Luis De La Fuente , Rajesh Vijayaraghavan
IPC分类号： G01R15/00 , G01R29/00 , G01R31/26 , G01N37/00 , H01L21/66 , G06F19/00
CPC分类号： G01R31/287
摘要： A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.
摘要翻译：一种方法包括接收与多个管芯相关联的第一组参数。基于第一组参数来确定与所选择的管芯相关联的第一管芯性能度量。基于第一组参数来确定与由与选定的管芯相邻的多个管芯组成的组相关联的至少一个邻近管芯性能度量。基于第一管芯性能度量和邻近管芯性能度量，为所选择的管芯确定第二管芯性能度量。

93. 发明授权

US06261885B1 Method for forming integrated circuit gate conductors from dual layers of polysilicon 有权
标题翻译：从双层多晶硅形成集成电路栅极导体的方法
公开(公告)号：US06261885B1
公开(公告)日：2001-07-17
申请号：US09497789
申请日：2000-02-03
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L218238
CPC分类号： H01L21/82345
摘要： A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region. The portion of the second polysilicon layer above the second active region and the portion of the first polysilicon layer above the second active region may be patterned to form a second gate structure within the second active region.
摘要翻译：提出了一种用于制造集成电路的方法，其中提供介于半导体衬底之上的第一多晶硅层。半导体衬底包含第一有源区和第二有源区。第一掺杂剂被选择性地引入第二有源区上方的第一多晶硅层的部分。然后可以在第一多晶硅层上并且在第一有源区和第二有源区上方形成第二多晶硅层。可以将第二掺杂剂选择性地引入第一有源区上方的第二多晶硅层的一部分。在第一有源区上方的第二多晶硅层的部分和第一有源区上方的第一多晶硅层的部分可以被图案化以在第一有源区内形成第一栅极结构。在第二有源区上方的第二多晶硅层的部分和第二有源区上方的第一多晶硅层的部分可以被图案化以在第二有源区内形成第二栅极结构。

94. 发明授权

US5770482A Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto 失效
公开(公告)号：US5770482A
公开(公告)日：1998-06-23
申请号：US727049
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
发明人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L21/00 , H01L21/84
CPC分类号： H01L21/8221 , H01L23/485 , H01L23/535 , H01L27/0688 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

95. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

96. 发明授权

US6150695A Multilevel transistor formation employing a local substrate formed within a shallow trench 失效
标题翻译：使用在浅沟槽内形成的局部衬底的多晶体管形成
公开(公告)号：US6150695A
公开(公告)日：2000-11-21
申请号：US741812
申请日：1996-10-30
申请人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/822 , H01L27/06 , H01L27/01
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：双级晶体管和制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在蚀刻到第一衬底间电介质中的局部沟槽内。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板和形成在全局基板上的第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一基板间电介质包括局部沟槽。第一局部衬底形成在局部沟槽内。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

97. 发明授权

US5783458A Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer 失效
标题翻译：具有氮化氧化物的非对称p沟道晶体管被图案化以允许选择形成生长侧壁间隔物
公开(公告)号：US5783458A
公开(公告)日：1998-07-21
申请号：US720731
申请日：1996-10-01
申请人： Daniel Kadosh , Robert Dawson , Fred N. Hause
发明人： Daniel Kadosh , Robert Dawson , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265 , H01L21/44
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current-a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

98. 发明授权

US5744371A Asymmetrical p-channel transistor having a boron migration barrier and LDD implant only in the drain region 失效
标题翻译：具有硼迁移势垒和仅在漏极区域中的LDD注入的非对称p沟道晶体管
公开(公告)号：US5744371A
公开(公告)日：1998-04-28
申请号：US720735
申请日：1996-10-01
申请人： Daniel Kadosh , Brad T. Moore
发明人： Daniel Kadosh , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

99. 发明授权

US07650199B1 End of line performance prediction 有权
标题翻译：行尾预测
公开(公告)号：US07650199B1
公开(公告)日：2010-01-19
申请号：US11196073
申请日：2005-08-03
申请人： Daniel Kadosh
发明人： Daniel Kadosh
IPC分类号： G06F19/00
CPC分类号： G05B19/41865 , G05B2219/32301 , Y02P90/20 , Y02P90/26
摘要： A method, apparatus, and a system for performing post processing modeling is provided. A predicted end of line parameter relating to a workpiece is determined. The predicted end of line parameter is stored. An interface for accessing the end of line parameters provided.
摘要翻译：提供了一种用于执行后处理建模的方法，装置和系统。确定与工件相关的预测行尾参数。存储预测的行尾参数。用于访问提供的行参数的结尾的接口。

100. 发明申请

US20080244348A1 DETERMINING DIE PERFORMANCE BY INCORPORATING NEIGHBORING DIE PERFORMANCE METRICS 有权
标题翻译：确定相邻性能性能指标的性能
公开(公告)号：US20080244348A1
公开(公告)日：2008-10-02
申请号：US11692989
申请日：2007-03-29
申请人： Daniel Kadosh , Gregory A. Cherry , Carl Bowen , Luis De La Fuente , Rajesh Vijayaraghavan
发明人： Daniel Kadosh , Gregory A. Cherry , Carl Bowen , Luis De La Fuente , Rajesh Vijayaraghavan
IPC分类号： G06F11/00
CPC分类号： G01R31/287
摘要： A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.
摘要翻译：一种方法包括接收与多个管芯相关联的第一组参数。基于第一组参数来确定与所选择的管芯相关联的第一管芯性能度量。基于第一组参数来确定与由与选定的管芯相邻的多个管芯组成的组相关联的至少一个邻近管芯性能度量。基于第一管芯性能度量和邻近管芯性能度量，为所选择的管芯确定第二管芯性能度量。

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