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91. 发明授权

US07012008B1 Dual spacer process for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的双间隔器工艺
公开(公告)号：US07012008B1
公开(公告)日：2006-03-14
申请号：US09728554
申请日：2000-12-01
申请人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
IPC分类号： H01L21/31
CPC分类号： H01L27/11568 , H01L27/11526 , H01L27/11531
摘要： In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.
摘要翻译：在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。植入后，沉积第二间隔物。在第二间隔物沉积之后，执行外围间隔物蚀刻。通过上述方法，形成间隔物。

92. 发明授权

US06927129B1 Narrow wide spacer 有权
标题翻译：狭窄的间距
公开(公告)号：US06927129B1
公开(公告)日：2005-08-09
申请号：US10821312
申请日：2004-04-08
申请人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
发明人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L29/6656 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall; etching the first oxide layer wherein a portion of the first oxide layer remains on the source side sidewall and on the drain side sidewall of the periphery transistor and on the source side sidewall and on the drain side sidewall of the core transistor; etching the first oxide layer from the source side sidewall of the core transistor; depositing a second oxide layer over the periphery transistor and the core transistor; and etching the second oxide layer wherein a portion of the second oxide layer remains on the first oxide layer formed on the source side sidewall and on the drain side sidewall of the periphery transistor and wherein the second oxide layer remains on the source side sidewall and on the drain side sidewall of the core transistor.
摘要翻译：一种半导体器件的制造方法。具体地说，一种制造半导体器件的方法，包括：在包括栅极堆叠，漏极侧壁和源极侧壁的外围晶体管上沉积第一氧化物层，以及包括栅极堆叠，源极侧壁和排水侧壁蚀刻第一氧化物层，其中第一氧化物层的一部分保留在外围晶体管的源极侧壁和漏极侧壁上，并且在芯晶体管的源极侧壁和漏极侧侧壁上残留; 从芯晶体管的源极侧壁蚀刻第一氧化物层; 在外围晶体管和芯晶体管上沉积第二氧化物层; 以及蚀刻所述第二氧化物层，其中所述第二氧化物层的一部分保留在形成在所述外围晶体管的源极侧壁和漏极侧壁上的第一氧化物层上，并且其中所述第二氧化物层保留在所述源侧侧壁上，芯晶体管的漏极侧壁。

93. 发明授权

US06727143B1 Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation 有权
标题翻译：在层间电介质形成中使用ARC层时降低电荷增益和电荷损失的方法和系统
公开(公告)号：US06727143B1
公开(公告)日：2004-04-27
申请号：US09533619
申请日：2000-03-22
申请人： Angela T. Hui , Mark T. Ramsbey , Yu Sun , David H. Matsumoto
发明人： Angela T. Hui , Mark T. Ramsbey , Yu Sun , David H. Matsumoto
IPC分类号： H01L218242
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The method and system further include providing an antireflective coating (ARC) layer. At least a portion of the ARC layer is on the interlayer dielectric. The method and system further include providing a plurality of via holes in the interlayer dielectric and the ARC layer and filling the plurality of via holes with a conductive material. The method and system further include removing the ARC layer while reducing subsequent undesirable charge gain and subsequent undesirable charge loss over the use of a chemical mechanical polish in removing the ARC layer.
摘要翻译：公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。该方法和系统包括在下层上提供层间电介质。该方法和系统还包括提供抗反射涂层（ARC）层。 ARC层的至少一部分在层间电介质上。该方法和系统还包括在层间电介质和ARC层中提供多个通孔，并用导电材料填充多个通孔。该方法和系统还包括去除ARC层，同时减少随后的不期望的电荷增益和随后的不期望的电荷损失，使用化学机械抛光剂去除ARC层。

94. 发明授权

US06680507B2 Dual bit isolation scheme for flash memory devices having polysilicon floating gates 失效
标题翻译：具有多晶硅浮动栅极的闪存器件的双位隔离方案
公开(公告)号：US06680507B2
公开(公告)日：2004-01-20
申请号：US09833307
申请日：2001-04-11
申请人： Tuan Pham , Angela T. Hui
发明人： Tuan Pham , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , G11C16/0458 , H01L27/11521
摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.
摘要翻译：本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。还公开了用于制造根据本发明的存储器件的工艺。

95. 发明授权

US06664191B1 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
标题翻译：非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
公开(公告)号：US06664191B1
公开(公告)日：2003-12-16
申请号：US09973131
申请日：2001-10-09
申请人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
发明人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
IPC分类号： H01L21302
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/76229 , H01L21/76838 , H01L27/11531 , Y10S438/975
摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
摘要翻译：提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。第一多晶硅层沉积在覆盖STI区域的衬底上。然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

96. 发明授权

US06664180B1 Method of forming smaller trench line width using a spacer hard mask 有权
标题翻译：使用间隔物硬掩模形成较小沟槽宽度的方法
公开(公告)号：US06664180B1
公开(公告)日：2003-12-16
申请号：US09824415
申请日：2001-04-02
申请人： Angela T. Hui , Bhanwar Singh
发明人： Angela T. Hui , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76816 , Y10S438/952
摘要： An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.
摘要翻译：形成沟槽线的示例性方法包括在抗反射涂层（ARC）层上提供光致抗蚀剂图案，其中ARC层沉积在材料层上; 根据光致抗蚀剂图案蚀刻ARC层以形成ARC特征; 在ARC特征的侧面上形成间隔物; 并且使用间隔物和ARC特征蚀刻沟槽线作为硬掩模以限定蚀刻的材料层的部分。

97. 发明授权

US06589841B1 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate 失效
公开(公告)号：US06589841B1
公开(公告)日：2003-07-08
申请号：US10180772
申请日：2002-06-25
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

98. 发明授权

US06514868B1 Method of creating a smaller contact using hard mask 有权
标题翻译：使用硬掩模创建较小接触的方法
公开(公告)号：US06514868B1
公开(公告)日：2003-02-04
申请号：US09817911
申请日：2001-03-26
申请人： Angela T. Hui , Bhanwar Singh
发明人： Angela T. Hui , Bhanwar Singh
IPC分类号： H01L2100
CPC分类号： H01L21/76816 , H01L21/31144
摘要： An exemplary method is described which forms a contact hole having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a contact hole is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a contact hole using the hard mask to transfer the second critical dimension to the contact hole.
摘要翻译：描述了一种示例性方法，其形成具有临界尺寸的接触孔，临界尺寸小于可能使用常规光刻技术的临界尺寸。该方法可以包括在要形成接触孔的材料层上提供硬掩模; 在硬掩模的顶部以第一临界尺寸蚀刻硬掩模，在硬掩模的底部蚀刻第二临界尺寸; 以及使用所述硬掩模蚀刻接触孔以将所述第二临界尺寸转移到所述接触孔。

99. 发明授权

US06506683B1 In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers 有权
标题翻译：用于制造具有整体去除抗反射和蚀刻停止层的半导体器件的原位工艺
公开(公告)号：US06506683B1
公开(公告)日：2003-01-14
申请号：US09413621
申请日：1999-10-06
申请人： Angela T. Hui , Yongzhong Hu
发明人： Angela T. Hui , Yongzhong Hu
IPC分类号： H01L21302
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/31116 , H01L21/76816 , H01L21/76895 , H01L27/115
摘要： A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer. The photoresist layer is removed, and the antireflection layer and portions of the etch stop layer which underlie the third holes are simultaneously removed to form fourth holes through the etch stop layer without adversely affecting the insulator layer and/or the interconnect areas. The third and fourth holes are then filled ex-situ with electrically conductive tungsten which ohmically contacts the interconnect areas to form local interconnects. The simultaneous removal of the antireflection layer and the portions of the etch stop layer eliminate several conventional processing steps and enable much of the processing to be performed in-situ.
摘要翻译：诸如闪存电可擦除可编程只读存储器（闪存EEPROM）的半导体存储器件通过原位执行多个工艺步骤来制造。具有局部互连区域的半导体器件形成在半导体衬底的表面上。在衬底和器件的表面上形成蚀刻停止层，并且在蚀刻停止层上形成层间电介质层（ILD）。在绝缘体层之上形成抗反射层（ARC），并且在绝缘体层上形成光致抗蚀剂层。光致抗蚀剂层被光刻图案化以形成穿过其的互连区域的第一孔。使用图案化的光致抗蚀剂层作为掩模，使用通过抗反射层的反应离子蚀刻（RIE）蚀刻到第一孔的第一孔的第二孔到绝缘体层。通过绝缘体层蚀刻第三个孔直到蚀刻停止层。去除光致抗蚀剂层，并且防反射层和位于第三孔下面的蚀刻停止层的部分被同时去除，以通过蚀刻停止层形成第四孔，而不会不利地影响绝缘体层和/或互连区域。然后，第三和第四个孔被非导电钨填充，导电钨与互连区域欧姆接触以形成局部互连。同时去除抗反射层和蚀刻停止层的部分消除了几个常规的处理步骤，并且使得大部分处理能够在原位进行。

100. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

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