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91. 发明授权

US07034560B2 Device and method for testing integrated circuit dice in an integrated circuit module 失效
公开(公告)号：US07034560B2
公开(公告)日：2006-04-25
申请号：US10801254
申请日：2004-03-16
申请人： Warren M. Farnworth , James M. Wark , Eric S. Nelson , Kevin G. Duesman
发明人： Warren M. Farnworth , James M. Wark , Eric S. Nelson , Kevin G. Duesman
IPC分类号： G01R31/28
CPC分类号： G11C29/785 , G01R31/2884 , G01R31/31701 , G01R31/31719 , G01R31/318513 , G11C29/1201 , G11C29/46 , G11C29/80 , G11C29/808 , H01L22/22 , H01L2224/48091 , H01L2224/48227 , H04J2203/0062 , H01L2924/00014
摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

92. 发明授权

US07026835B2 Engagement probe having a grouping of projecting apexes for engaging a conductive pad 失效
标题翻译：接合探针具有一组突出的顶点，用于接合导电垫
公开(公告)号：US07026835B2
公开(公告)日：2006-04-11
申请号：US10232295
申请日：2002-08-30
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： An exemplary engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate is described. Constructions are disclosed for testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：描述了具有外表面的示例性接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，以与半导体衬底上的单个测试焊盘接合。公开了一种用于包括接合探针的测试装置的结构，所述接合探针的外表面包括彼此靠近定位的多个导电突起顶点的组，以接合半导体衬底上的单个测试焊盘。

93. 发明授权

US07021915B2 Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length 失效
公开(公告)号：US07021915B2
公开(公告)日：2006-04-04
申请号：US10987843
申请日：2004-11-12
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L21/56 , B29C41/20
CPC分类号： B29C64/135 , B29C2035/0838 , B29C2037/903 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , B33Y40/00
摘要： An apparatus and method for controlling the surface level of a liquid residing within a relatively vertically stationary workpiece support platform disposed within a reservoir for use in stereolithographic processes wherein a layered object or structure is formed by selectively curing portions of the liquid to at least a semisolid state in multiple, at least partially superimposed layers. Providing precise control of liquid depth over the vertically stationary platform as well as focusing of a laser beam for curing the liquid at the varying surface levels thereof relative to the vertically stationary platform is effected using a laser range finder system controlled by a computer used to control the stereolithographic process in a closed loop fashion.

94. 发明授权

US07003874B1 Methods of bonding solder balls to bond pads on a substrate 失效
标题翻译：将焊球焊接到基板上的接合焊盘的方法
公开(公告)号：US07003874B1
公开(公告)日：2006-02-28
申请号：US09148723
申请日：1998-09-03
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H05K3/34 , B23K31/02
CPC分类号： H01L21/67138 , B23K1/0056 , B23K2101/42 , H01L21/4853 , H01L2224/11334 , H05K3/3478 , H05K3/3494 , H05K2203/041 , H05K2203/043 , H05K2203/0557 , H05K2203/107 , Y10T29/49144 , Y10T29/49149 , Y10T29/49179
摘要： Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame and in registered alignment with individual bond pads over a substrate. While the ball portions are within the frame, the balls are exposed to bonding conditions effective to bond the balls with their associated bond pads. In another embodiment, a frame is provided having a plurality of holes sized to receive individual solder balls. Individual balls are delivered into the holes from over the frame. The balls are placed into registered alignment with a plurality of individual bond pads over a substrate while the balls are in the holes. The balls are bonded with the individual associated bond pads. In another embodiment, a frame is provided having a hole. A solder ball is provided having an outer surface. The solder ball is retained within the hole in an ambient processing environment which is generally uniform over the entirety of the ball's outer surface. While the solder ball is within the hole, the solder ball is bonded with an associated bond pad on a substrate.
摘要翻译：描述了将焊球焊接到接合焊盘的方法和装置。在一个实施例中，多个焊球的部分被放置在框架内并且与衬底上的各个接合焊盘对齐配准。当球部分在框架内时，球暴露于有效地将球与其相关联的接合垫结合的粘合条件。在另一个实施例中，提供一个框架，其具有多个孔，其尺寸适于接收单独的焊球。单个球从框架上传送到孔中。当球在孔中时，将球放置成与衬底上的多个单独接合焊盘配准对齐。球与各个相关联的接合垫结合。在另一个实施例中，提供具有孔的框架。提供具有外表面的焊球。焊球在环境处理环境中保持在孔内，该环境处理环境在整个球的外表面上通常是均匀的。当焊球在孔内时，焊球与衬底上的相关联的焊盘接合。

95. 发明授权

US06980017B1 Test interconnect for bumped semiconductor components and method of fabrication 失效
标题翻译：凸起半导体元件的测试互连和制造方法
公开(公告)号：US06980017B1
公开(公告)日：2005-12-27
申请号：US09266237
申请日：1999-03-10
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： G01R1/04 , H05K1/11 , H05K3/32 , H05K3/40 , G01R31/02 , G01R31/26
CPC分类号： H05K3/326 , G01R1/0466 , G01R31/2853 , H05K1/118 , H05K3/4092 , H05K2201/0373 , H05K2201/0397 , H05K2201/09036 , H05K2201/09081 , H05K2201/10734 , Y10T29/49117 , Y10T29/49121 , Y10T29/4913 , Y10T29/49139 , Y10T29/4914 , Y10T29/49155 , Y10T29/49165
摘要： An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.
摘要翻译：用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

96. 发明授权

US06980014B2 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06980014B2
公开(公告)日：2005-12-27
申请号：US10379221
申请日：2003-03-04
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , H05K1/11 , H05K1/14 , H05K3/34 , G01R31/02
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with a substrate. The fence may include edges that are configured to progressively align a semiconductor device with the substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，包括接收半导体器件（例如倒装芯片型半导体器件）和衬底的栅栏。栅栏可以包括被配置为逐渐地将半导体器件与衬底对准的边缘。栅栏还可以包括一个或多个侧向凹入的区域，以便于半导体器件与衬底的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备，并且有助于识别材料在其上和周围的位置和取向施加在一个或多个层中以形成栅栏。因此，基板不需要精确地机械对准。

97. 发明授权

US06979904B2 Integrated circuit package having reduced interconnects 失效
标题翻译：集成电路封装具有减少的互连
公开(公告)号：US06979904B2
公开(公告)日：2005-12-27
申请号：US10126067
申请日：2002-04-19
申请人： Warren M. Farnworth , Jerry M. Brooks
发明人： Warren M. Farnworth , Jerry M. Brooks
IPC分类号： H01L23/48 , H01L23/52 , H01L25/065 , H01L29/40
CPC分类号： H01L25/0657 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
摘要翻译：一种制造集成电路封装的技术。具体地，堆叠的存储器件具有最小的互连。存储器管芯彼此堆叠并电耦合到衬底。通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。线键用于完成电路封装。

98. 发明授权

US06979898B1 Semiconductor component and a method of fabricating the semiconductor component 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US06979898B1
公开(公告)日：2005-12-27
申请号：US09420086
申请日：1999-10-18
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/48 , H05K3/02 , H01L23/04 , H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/3128 , G01R1/0483 , G01R3/00 , G01R31/2867 , H01L21/4846 , H01L23/32 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/72 , H01L2224/05554 , H01L2224/05599 , H01L2224/48227 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10161 , H01L2924/12042 , H01L2924/3011 , H01L2924/30111 , H05K1/0218 , H05K1/113 , H05K3/027 , H05K2201/09363 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor component and a method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The semiconductor component includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.
摘要翻译：提供了一种半导体元件和用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体之类的半导体元件的方法。半导体部件包括提供其上具有覆盖层的导电层的衬底。使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

99. 发明授权

US06974725B2 Interconnections for a semiconductor device 失效
标题翻译：半导体器件的互连
公开(公告)号：US06974725B2
公开(公告)日：2005-12-13
申请号：US10808713
申请日：2004-03-23
申请人： Walter L. Moden , Larry D. Kinsman , Warren M. Farnworth
发明人： Walter L. Moden , Larry D. Kinsman , Warren M. Farnworth
IPC分类号： H01L23/31 , H01L23/485 , H01L21/44
CPC分类号： H01L24/10 , H01L23/3107 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/05568 , H01L2224/05573 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/85399 , H01L2224/8592 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/00014 , H01L2924/00 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00013 , H01L2924/013
摘要： A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.
摘要翻译：一种用于形成用于半导体器件的电接触的方法包括以下步骤：提供具有主表面的半导体晶片部分，其上具有多个导电焊盘，并使每个焊盘与细长的电互连电连接。接下来，每个电互连被封装在电介质中，并且电介质被分段以暴露每个互连的一部分。还描述了可以通过本发明方法形成的本发明的结构。

100. 发明授权

US06896837B2 Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length 失效
公开(公告)号：US06896837B2
公开(公告)日：2005-05-24
申请号：US10225945
申请日：2002-08-22
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： B29C35/08 , B29C67/00 , B29C41/02 , B29C70/72
CPC分类号： B29C64/135 , B29C2035/0838 , B29C2037/903 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , B33Y40/00
摘要： An apparatus and method for controlling the surface level of a liquid residing within a relatively vertically stationary workpiece support platform disposed within a reservoir for use in stereolithographic processes wherein a layered object or structure is formed by selectively curing portions of the liquid to at least a semisolid state in multiple, at least partially superimposed layers. Providing precise control of liquid depth over the vertically stationary platform as well as focusing of a laser beam for curing the liquid at the varying surface levels thereof relative to the vertically stationary platform is effected using a laser range finder system controlled by a computer used to control the stereolithographic process in a closed loop fashion.

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