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1. 发明授权

US06686758B1 Engagement probe and apparatuses configured to engage a conductive pad 失效
标题翻译：配置探针和配置成接合导电垫的装置
公开(公告)号：US06686758B1
公开(公告)日：2004-02-03
申请号：US09534822
申请日：2000-03-23
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R3102
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

2. 发明授权

US07026835B2 Engagement probe having a grouping of projecting apexes for engaging a conductive pad 失效
标题翻译：接合探针具有一组突出的顶点，用于接合导电垫
公开(公告)号：US07026835B2
公开(公告)日：2006-04-11
申请号：US10232295
申请日：2002-08-30
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： An exemplary engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate is described. Constructions are disclosed for testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：描述了具有外表面的示例性接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，以与半导体衬底上的单个测试焊盘接合。公开了一种用于包括接合探针的测试装置的结构，所述接合探针的外表面包括彼此靠近定位的多个导电突起顶点的组，以接合半导体衬底上的单个测试焊盘。

3. 发明授权

US06670819B2 Methods of engaging electrically conductive pads on a semiconductor substrate 失效
公开(公告)号：US06670819B2
公开(公告)日：2003-12-30
申请号：US10057711
申请日：2002-01-24
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R3102
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

4. 发明授权

US07116118B2 Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability 失效
标题翻译：用于测试可操作性的半导体电路的方法和装置以及用于测试半导体电路的可操作性的装置的方法
公开(公告)号：US07116118B2
公开(公告)日：2006-10-03
申请号：US10803264
申请日：2004-03-17
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

5. 发明授权

US06833727B2 Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability 失效
标题翻译：用于测试可操作性的半导体电路的方法和装置以及用于测试半导体电路的可操作性的装置的方法
公开(公告)号：US06833727B2
公开(公告)日：2004-12-21
申请号：US10803294
申请日：2004-03-17
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R3102
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conducive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供接合探针，其具有外表面，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

6. 发明授权

US5326428A Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability 失效
标题翻译：用于测试可操作性的半导体电路的方法和用于测试半导体电路的可操作性的装置的方法
公开(公告)号：US5326428A
公开(公告)日：1994-07-05
申请号：US716394
申请日：1993-09-03
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/26 , G01R1/073 , G01R31/02 , H01L21/66 , H01R43/00 , H05K1/03 , H05K3/32 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , H05K3/325 , Y10S438/978 , Y10T29/49117 , Y10T29/49204
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

7. 发明授权

US6127195A Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus 失效
标题翻译：形成用于接合导电垫的装置的方法和形成可拆卸的电互连装置的方法
公开(公告)号：US6127195A
公开(公告)日：2000-10-03
申请号：US895764
申请日：1997-07-17
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/26 , G01R1/073 , G01R31/02 , H01L21/66 , H01R43/00 , H05K1/03 , H05K3/32
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , H05K3/325 , Y10S438/978 , Y10T29/49117 , Y10T29/49204
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

8. 发明授权

US6124721A Method of engaging electrically conductive test pads on a semiconductor substrate 失效
标题翻译：在半导体衬底上接合导电测试焊盘的方法
公开(公告)号：US6124721A
公开(公告)日：2000-09-26
申请号：US962229
申请日：1997-10-31
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R31/26 , G01R1/073 , G01R31/02 , H01L21/66 , H01R43/00 , H05K1/03 , H05K3/32
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , H05K3/325 , Y10S438/978 , Y10T29/49117 , Y10T29/49204
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

9. 发明授权

US07098475B2 Apparatuses configured to engage a conductive pad 失效
标题翻译：被配置为接合导电垫的装置
公开(公告)号：US07098475B2
公开(公告)日：2006-08-29
申请号：US10703763
申请日：2003-11-07
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： H01L23/58 , G01R31/02
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

10. 发明授权

US06657450B2 Methods of engaging electrically conductive test pads on a semiconductor substrate removable electrical interconnect apparatuses, engagement probes and removable engagement probes 失效
标题翻译：在半导体衬底上接合导电测试焊盘的方法可移除的电互连设备，接合探针和可移除的接合探针
公开(公告)号：US06657450B2
公开(公告)日：2003-12-02
申请号：US09411139
申请日：1999-10-01
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R3102
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.
摘要翻译：一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组，半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

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